My area of functionality is working on the Strategic Intervention contents and doing research on the latest cutting-edge Leadership Breakthroughs across the globe. This, along with my industry experience of close to a decade in some of the biggest Corporates gives me a great insight in developing the contents which is customized and most applicable for the industry.

I am a member of Toastmasters International since June 2013. I am past Area Director for Area 4, Division M.Committee role:I served as the Secretary and VP-Education of Wipro EC Friday Toastmasters from November 2013 to December 2014, served as the President of Mecon Communication Club, was the Area Director for Area M4, District 92 from July 2018 to June 2019, was the Club Mentor for EC TM Club and Bosch TM Club. I was also the Communication Specialist for Tarento TM Club.Awards and recognitions so far:Distinguished Toastmaster Won the Conference Naming Contest - Eloquence - 2014, Division D,District 82Educational Awards - ACS and ALBWas awarded the Triple Crown at Jamboree, Semi Annual Conference, District 92First runner-up at the Club Level of the Humorous Contest held in 2014.Second runner-up at the Club Level of the International Speech Contest held in 2015.First runner-up at the Club Level of the Table Topics Contest held in 2018.Educational Sessions given so far :1. Evaluate to Motivate (Wipro TM Club, Siemens TM Club, Flowserve TM Club, Yokogawa TM Club and CGI TM Club)2. Speech Writing (Wipro TM Club, NUK TM Club and Siemens TM Club)3. Get to the point (SKF TM Club)

Responsibilities• Implemented the client-specific verification flow for verification of SoC Level modules.• Performed Verification of Analog blocks(PLLs, EBICDC, SDCCDC) through using System Verilog.• Led to implement EBICDC and SDCCDC by using the TLMM GPIO muxing.• Oversaw the RTL functional verification of EBICDC and SDCCDC blocks.Responsibilities• Implemented the TI-SoC verification flow for verification of Champion modules.• Oversaw the Verification of system modules (Vectored Interrupt Module and Cyclic Redundancy Checker)using Unified Assembly Language.• Led to Verification of peripheral modules (Serial Communication Interface) using Unified Assembly Language.• Implemented the Pin muxing for the peripheral module SCI as per specification.• Tested the SCI uses power domain 3. VIM and MCRC use power domain 1.• Managed the RTL and Gate Level Simulation (GLS) of SCI, VIM, MCRC, PMT. and DVE simulator.• Utilized the BIST FTDL of SCI, VIM, and MCRC. NON BIST FTDL of DCAN2, DCAN3, VIM, and ESM.

Responsibilities• Developed chip-level verification environment and performed verification• Prepared the Design document for System Packet Interface• Designed the Configuration & Status register interface For SPI – 5 & user interface• Performed the design & RTL Coding of the user interface using Verilog• Led to Synthesis and Place & Route using Xilinx ISE• Oversaw the Simulation through using ModelSim for The target device is Virtex-4 FPGA

FALCON_FPGA Platform board basic functionality testing WSPI– DTV Designing an interface between RS codec and modem