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Micro-architecture engineer with hands-on experience in architecture, design, integration, & silicon-validation of complex analog systems in SoC-FPGAs products. • Projects: Intel Agilex, Xilinx Versal Processing System (PS), Xilinx Zynq UltraScale+ PS, & Zynq 7000 PS, Stratix V, Cyclone -V.• In-depth design knowledge of Serdes, LPDDR4, DDR4 Phy, PLLs, IOs, System monitor ADC, RTC, and PUF.• Managed and owned technical engagements with 3rd party IP vendors of Serdes, DDR-phy, & IOs through complete design-cycle: IP requirements definition, Evaluations, Design implementation, Tape-out sign-offs, and post Si validation.• Expertise in analog mixed-signal co-simulation using RNM, Verilog AMS, & Spice netlist.• In-depth knowledge of Signal and Power integrity for SerDes, DDR, & IOs. • Timing budget analysis for DDR4/LPDDR4 interfaces.• Owned Si validation and char strategy definition and execution for complex analog systems.• 6 awarded patents in field of Serdes and PLL architecture in FPGAs.• Knowledge of Security and Functional safety for analog systems for ASIL-C certification.• Experience in Reliability: ESD, EOS, HTOL, Self-heating, Aging, Latch-up, and FA debug and testing.• Strong leadership and teamwork in resolving issues.• Experienced in managing contractors and engineers across geographies.Tools & Languages:Hardware Description Languages: SystemVerilog, ChiselSoC and NoC Design Tools: Magillem, Arteris FlexNoCSynthesis and Verification Tools: Design Compiler, VC-Spyglass, PrimeTime, FishtailSimulation and Debug Tools: VCS, Verdi, DVE, VCS-XA Cosim, UVM test-benchProgramming and Scripting Languages: Perl, Python, Scala, SKILL, TCL, MatlabLab testing: Oscilloscope | Bert-scope | Protocol analyzersSignal Integrity: ADS, Allegro, IBIS modelFPGA: Quartus, Vivado, Vitis
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Chip TechnologistIntel CorporationSan Jose, Ca, Us -
Micro-Architecture EngineerAltera Jan 2024 - PresentSan Jose, California, Us- Led RTL integration of IPs for Secure Device Manager at the SoC level, including ADC, IOs, PUF, NoC, and AMS IPs (PLLs, Clock/Reset controls).- Designed SAR-based ADC Controller for 10-bit 1 MSps on-chip VT monitoring, micro-architecting control FSM for calibration, acquisition timing, channel sequencing, FIR filter-based averaging, and VT excursion alarms. Integrated PMbus/I2C bridge for register access..- Performed RTL Lint, CDC, RDC, and CLP checks using VC-Spyglass, ensuring clean design handoff to the physical design team.- Defined and managed SDC timing constraints for synthesis (Design Compiler) and timing analysis (PrimeTime) to achieve robust timing closure. Verified constraints using FishTail.- Developed micro-architectural specifications with detailed block and timing diagrams.- Collaborated with the verification team to review test plans, coverage analysis, and support UVM-based testing.- Expertise in mixed-signal verification, verifying SoC boot modes in AMS simulations and developing MS & RNM models for key AMS IPs for faster co-simulations with the digital SoC top DUT.- Supported PPA iterations with the Physical Design team, contributing to design partitioning, floor-planning and achieving timing, power, and performance goals.- Implemented DFX features, including scan and ATPG control, to enhance testability.- Worked cross-functionally with architecture, DV, firmware, physical design, and silicon validation teams. -
Sr Staff Design EngineerIntel Corporation 2019 - Dec 2023Santa Clara, California, UsOwned Full chip ESD, SEL and LU reliability and testing for Agilex
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Sr. Staff Design EngineerXilinx 2013 - 2019San Jose, Ca, UsProjects: Versal SoC Development at 7nm & Zynq UltraScale+ SOC Development at 16nm ● RTL design and Integration of analog blocks into SoC using System-Verilog.● Analog IPs Integrated: ○ Serdes Phy: PCIe Gen3/2/1, USB 3.0, IEEE/802.3, DisplayPort v1.2. ○ DDR Phy: LPDDR4, DDR4, DDR3, DDR3L. ○ Analog IPs: Clocking PLLs, IOs, System monitor ADC, RTC, & PoR.● Managed technical engagement for SerDes, DDR-phy, & IO vendors for PS block in Zynq US+.● Developed concise engineering micro-architecture specifications.● Reviewed Verification test-plans and coverage analysis.● Performed RTL Lint, CDC, & RDC checks.● Designed for low-power multi-domain architecture and did UPF coding and CLP checking.● Define SDC timing constraints in TCL for synthesis and timing analysis.● Implemented ATE DFX requirements support: DFT, design for reliability, and design for char.● Owned Si-validation plan and execution for SerDes Phy and DDR-IOs.● Verified SoC boot-modes in mixed-signal simulations. Developed test-benches with digital top and mixed-mode models in RNM, Verilog-AMS, and Spice for lower-level modules.● Developed key entropy-source for secure physical-unclonable function (PUF) in 16nm and 7nm.● Analyze and Sign-off timing-budget for DDR4/LPDDR4 2667Mbps interfaces.● Defined requirements for in-house test-boards and test-plans.● Analyzed EMIR drop based on VCD-driven transient current load.● Simulated jitter for Serdes, DDRIOs, and SSN for low-speed IOs.● Provided PCB design guidelines for target impedance and PCB decaps.● Involved in FMEDA analysis for Functional safety to achieve ASIL-C certification. -
Sr. Mts Design EngineerAltera 2001 - 2013San Jose, California, UsProject: Serdes Architecture definition and integration in Stratix-V and Cyclone-V [2009 - 2013]● Analyzed and proposed architecture specifications for Serdes blocks based on customer use-cases. Serdes architecture patents issued for Stratix V and Cyclone V.● Defined Serdes modularity, clocking architecture between PMA-PCS and PCS-PL-fabric interfaces.● Design and validate SI/PI to support PCIe Gen2 in Cyclone-V GT devices in Wire-bond package.● Designed Serdes-PLD fabric interface to run >300MHz.Project: PLL IP design in Altera Apex-II HardCopy Products in 65nm and 90nm ● Led circuit design of PFD-CP and Integration of PLL into HC-I & HC-II devices. ● Developed Matlab model for PLL stability and Jitter prediction. Project: Low-cost Serdes design in Altera Apex-II HardCopy Products in 90nm ● Design 3 GB/s CML TX buffer for PCIe and XAUI ● Design current-steering Phase-DAC (Interpolator) design.
Surinder S. Skills
Surinder S. Education Details
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Scpd, Stanford UniversityAnalog Design -
Delhi UniversityElectronics
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Delhi UniversityElectronics
Frequently Asked Questions about Surinder S.
What company does Surinder S. work for?
Surinder S. works for Intel Corporation
What is Surinder S.'s role at the current company?
Surinder S.'s current role is Chip Technologist.
What is Surinder S.'s email address?
Surinder S.'s email address is su****@****ail.com
What schools did Surinder S. attend?
Surinder S. attended Scpd, Stanford University, Delhi University, Delhi University.
What skills is Surinder S. known for?
Surinder S. has skills like Fpga, Analog, Serdes, Asic, Soc, Static Timing Analysis, Signal Integrity, Physical Design, Eda, Analog Circuit Design, Circuit Design, Pll.
Who are Surinder S.'s colleagues?
Surinder S.'s colleagues are Alvaro Mora, Ashley Goernitz, Dustin Lacbain, Vicky Venditto, Andrew Mcguire, Robert Mccaskey, Kathy Mccarthy.
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