1) Turnkey Design Verification Development : test and coverage plan writing, UVM environment build up, VIP integration, direct and constrained random test case writing, coverage (functional, assertion, code), scripting, version control 2) Assertion Based Verification using System Verilog Assertions (SVA)3) Universal Verification Methdology (UVM)4) PCIe and Ethernet protocols5) Xilinx FPGA (in progress)6) experienced in CPU, networking, SOC, and block level verification

Developed technical demos to demonstrate features in VMware Blockchain.

(formerly Oski Technology)1) Evangelized the power of formal verification to tackle deep corner case bugs, especially in complex control paths that simulation cannot hit easily 2) Introduced formal driven coverage to engineers accustomed to simulation driven coverage, including SystemVerilog Assertions (SVA), and differences in usage between formal and simulation 3) Introduced formal verification techniques such as black boxing to improve performance of formal engines4) Support formal engines from Synopsys, Cadence/Jasper, and Mentor

(formerly Mentor Graphics)1) Deployed Questsim's early SystemVerilog, SystemVerilog Assertions, and UPF low power technologies 2) Evangelized Mentor's early capabilities in cache coherency verification 3) Evangelized and deployed Mentor's "out of the box" formal verification methodologies such as structural design checks4) Drove the unification of Mentor's three major platforms : High Level System Level Platform, RTL Verification Platform, and Emulation Platform

1) Deployed VMM and RVM (pre-cursor to UVM) methodologies, with ARM AXI VIP, on customer system level designs based in Korea and Taiwan2) Deployed Vera High Level Verification language on customer Verilog and VHDL designs, using OOP framework to build scalable test bench 3) Paid consulting on multiple design verification projects at global tier 1 design companies based in the US, Asia, and Europe4) published "Validating physical access layer of WiMAX using SystemVerilog" paper on IEEE at https://ieeexplore.ieee.org/author/38191820100

(formerly VLSI Technology)1) Implemented exportable version of VLSI's triple DES cipher chip. RTL coded in VHDL. Tests written in ARM assembly code. Simulation using Modelsim. Synthesis and timing using Synopsys Design Compiler. Chip passed FIPS certification on first pass.2) Implemented "delayed transaction" on PCI Slave block for a large North Bridge system controller Co-created initial specifications. RTL coded in VHDL. Tests written in ARM assembly code and used Flexlm PCI models. Simulation using Modelsim. Synthesis and timing using Synopsys Design Compiler.

1) Implemented the Enhance Event ProcessorArray (EEPA) on MCS-196 based microcontroller. RTL design coded in iHDL. Simulation using Dylink environment, MCS-196 assembly code. Schematic entry using SEES. Timing using CAPCHK and BVRGEN.2) System validation of Intel's 386EX embedded processor, including DMA, System Controller, I/O paths.3) Improve fault grading of Intel's 186EC processor, writting X86 assembly code, simulations on Zycad Mach.