Srinivasan Venkataramanan Email & Phone Number

Bengaluru, Karnataka, IN

Chief Technology Officer (CTO) at VLSI ecosystem firm CVC (www.cvcblr.com).

Excited to assist Shankar and his team on the Semiconductor vertical.

Serving the worldwide DV community by reviewing contributions to DVCon US 2024.

Chicago, IL, US

Privileged to be part of the Program Committee for Design Automation Conference 2024 - Front-End Design in 2024.

Humbled and satisfied to have been invited to serve as part of TPC team at next year's DVCon USA edition. Year after year we strive very hard to keep the quality of submissions very high at this prestigious conference.

Chicago, IL, US

Part of Engineering Track, responsible for reviewing quality of submissions, timely reviews and feedback to authors

Chicago, IL, US

Serving as technical reviewer for papers coming from worldwide industry experts in Design Verification domain

New venture from CVC, a new platform to share Design-Verification News from around the globe, see: www.verifnews.org Contact me via email if you want to contribute to this new venture!

Excited to be serving Technical Program Committee (TPC) at DVCon India 2019

Excited to be serving upcoming DVCon China 2017 edition!

Serving as TPC member

Visiting faculty at SOIS Manipal

Serving as an active reviewer, member of TPC team with Ambar, Shankar et al. for DVCon USA 2016.

Coordinator at IEEE-SA India Focus Area: Encouraging more participation in IEEE standards in the filed of VLSI & EDA such as SystemVerilog, LowPower, VHDL, SystemC, E, PSL etc.

Elected to be vice chair of the most powerful & capable functional verification language - IEEE 1647, E language. Seeking active contributors to grow this language and expand the ecosystem.

San Jose, CA, US

Assist SoC Verification customers in India region with Trek from Brekersystems. Promoted Graph Based Verification in local community

Excited to bring DVCon to India through Accellera to serve the wide community of ASIC & FPGA design & verification teams in this part of the globe. See public endorsement of my contribution to this at: https://www.youtube.com/watch?v=-6Nnpa5BkTk For well over a decade, Indian engineers had to travel aborad to present their work in vendor neutral DV.

US

Helping local customer deployments, driving new evaluations for this exciting technology "Assertion Synthesis"

Sunnyvale, California, US

Consultant for various verification challenges across customers. Internally own and drive new verification technologies and methodology. Create collaterals, white papers, articles on interesting topics and motivate a team of 70+ CAEs from a technical standpoint.

Sunnyvale, California, US

Assembled a highly effective CAE team and lead them on technical front and also the people management part. Motivated the team to provide support to leading edge semiconductor design companies on their verification methodologies and challenges in various domains such as image processing, networking & processor design verification. My team was the GOTO team.

Joined S3 (Software & Silicon System, an Intel company) as part of Ethernet Switching Division. Introduced Specman based verification amidst strong incumbent, PLI based env. Learnt e from our Israel team, deployed it for the new blocks of a new monster chip: 10M+ complex Ethernet L2/L3 switch/router. Introduced concept of functional coverage, constrained.

Lead Verification engineer to VoIP SoC. Responsible for sub-system and full chip RVE environment. Developed BFM & testcases for UTOPIA, integrated to RVE env. Understood RVE from Ramnath and was leading its maintenance, upgrade.Brought up Mixed HDL flow with Modelsim to enable system level verification. Brought in several optimizations to make the sims.

Amsterdam, Noord-Holland, NL

Worked as part of Philips BU @ Caen (near Paris, France). During first project I worked on Emulation (Quicktrun) and pre-Si verification using VHDL for Digital Camera product line. In the second/derivative project, architected, designed and verified Image processing algorithm for next generation Web camera. Coded RTL using VHDL, verified with various test.

Eindhoven, Noord-Brabant, NL

During my Masters @IITD, Philips Sponsored my PG and I worked on IEEE-1364 (FireWire) project from Philips Albuquerque (New Mexico, USA). I worked at Philips Semiconductors, Microtel group in Eindhoven (Natlab premises). Worked on mixed-HDL sim flow, evaluated NC-CoEx (NCSIM, modern day IUS) first/Alpha/Beta versions. Recognized as the SIM expert across.

M.Tech, Vlsi Design (Vdtt)

Bachelor Of Engineering, Ee