A dynamic technical evangelist in the domain of VLSI design, with a base in the UK, US (San Jose), and India. My areas of interest are advanced verification solutions and methodologies such as SystemVerilog, UVM, OVM, VMM, Assertion-Based Verification, formal verification, etc. As CTO @CVC (www.cvcblr.com) my job is to streamline all the technical deliverables, meet customer expectations, and define the roadmap for the near future. I provide support to leading-edge semiconductor design companies on their verification methodologies and challenges. I have the right mix of both the Design house and EDA industry and hence can appreciate the strengths and weaknesses of both. In my previous employment with various design houses, I was actively involved in the verification of leading-edge high-speed, multi-million gates ASIC designs. I hold a Master's Degree from the prestigious Indian Institute of Technology (IIT), Delhi in VLSI Design, and a bachelor's degree in Electrical engineering from TCE, Madurai. I'm passionate about almost everything I do and that's really what drives me to excel. I'm generally peace-loving, soft-spoken individual except when it comes down to technical stuff - no compromise!Specialties: Co-authored the following books: - A Pragmatic Approach to VMM Adoption- Using PSL/Sugar, 2nd Edition and - SystemVerilog Assertions Handbook.(http://www.systemverilog.us)Contributing author in:The Functional Verification of Electronic Systemshttp://www.amazon.com/Functional-Verification-Electronic-Systems-Handbook/dp/1931695318 Presented in various forums such as DesignCon (East), DVCon, SNUG etc. Deliver trainings on SVA, SVTB, OVM, UVM, and VMM to customers.