An accomplished M.Tech graduate in Microelectronics and VLSI from IIT Hyderabad with a CGPA of 8.6. Experienced Lead RTL Design Engineer at GPMU Semiconductors with expertise in ASIC RTL design, synthesis, lint, CDC, functional verification with AMS simulations. Proficient in Verilog, System Verilog, and various EDA tools, with a solid background in developing RTL codes, debugging, and performing MS simulations. Demonstrated leadership skills in training teams and presenting at tech exhibitions. My expertise extends to I2C, OTP trimming blocks, and register based interfaces, complemented by strong conceptual knowledge of STA, timing closure, and protocols such as AMBA APB.Received appreciation and a bonus for consistently meeting project deadlines and exceeding expectations. Author of publication "Fabrication of Si Membrane using Frontend Bulk Micromachining".