⇨ I introduced the TEP (Technology Enabling Project) concept for IOT-based industrial platforms, resulting in 167 Design Wins from 122 Customers.⇨ I led the co-development of Intel's first IOT-based SOC with key Tier1 customers; powering on customer platforms within a week.⇨ I addressed 200+ customer issues related to BIOS, Platform, Ethernet, Graphics/Displays, PMC, OS, and other FW/SW issues, establishing expertise in system debugging.⇨ I received multiple DRAs and GRAs for the initiative, acknowledged for the successful PRQ and production launch of additional IOT-based SOC SKUs.Skillsets: Project Leadership, Customer Collaboration, Platform Power-On, System Debugging, Technical Validation

⇨ I served as a Chief Architect for the First Safety Island, leading a team of 20 engineers and defining detailed interfaces between Safety Island, CPU, PCH, and external MCUs.⇨ I successfully delivered critical FuSa features for Denverton-AD micro-server Intel's FuSa-based SOCs, contributing to winning Bosch and BMW’s business.⇨ I led FuSa Post-Si verification team, developing verification strategies deployed in six new Intel FuSa products, opening up a ~$XB business opportunity.⇨ I played a crucial role in evaluating and integrating the acquisition of "Yogitech" into Intel, facilitating team integration and aligning with Intel's validation flow.Skillsets: Functional Safety Technologist, SOC Architecture, Pre/Post-Si Validation Strategy, Test Plan, Complex Problem Solving, Influencer, Customer Engineering support, IOT System, Team Leader, Strategic Consulting

⇨ I led validation efforts for IVI platforms based on Valley View SoC and a VLV System-In-Package product, implementing risk-based validation methodologies critical to identifying performance bottlenecks.⇨ I developed post-Si Global Validation Plan/Strategy, Gap Analysis, Test Plans, and Test Contents for 10+ IOTG Platforms.⇨ I proposed DFx hooks and debug experiments, establishing a reputation as a highly solicited debug expert in the lab.⇨ Awarded DRA (2012) for accelerating and applying ASD use cases for Valley View A0 Tape In evaluation and validation readiness for IVI applications.Skillsets: In-Vehicle Infotainment (IVI), Validation Methodologies, Global Validation Planning, Debug Expertise, Automotive Platform/System

⇨ I designed and architected the PCIe Transaction Layer for the Kyrene Chipset, Intel's first PCIe-based chipset.⇨ I developed the A-Spec/HAS, encompassing signal interfaces, rules, protocols, control and data path logic, decoding logic, arbitration logic, data packing logic, error trapping, etc.⇨ I implemented the most intricate logic solutions for all supported configurations, demonstrating a comprehensive understanding of the design requirements.⇨ I formulated a proposal for managing MSIs, interrupts, and messages, and created complete RTL code from scratch.⇨ I applied the same design principles to subsequent projects, contributing to their successful execution.⇨ I engaged in RTL design using VHDL/Verilog, Synthesis with Design Compiler (DC), Timing analysis with Prime-time, Validation using Modelsim, and post-Si debugging utilizing Emulation on Quickturn.Skillsets: PCIe Design, A-Spec/HAS Development, Logic Solution, RTL Coding (VHDL/Verilog), MSI and Interrupt Handling, Project Consistency, RTL Design Tools (VHDL, Verilog, DC, Prime-time, Modelsim), and Pre/Post-Si Debugging (Quickturn)