Accomplished, self-motivated professional offering significant engineering experience to research and development arenas. Experienced in RTL and CMOS ASIC physical design and verification. Demonstrated talent designing and debugging complex mixed signal designs. Strong focus on schedule and technical detail. Proven multitasking and prioritizing abilities. Compute Systems: Linux/UNIX. Scripting Languages: KSH, BSH, Ruby, TCL, awk, sed. Database Query: SQL. IC Design tools: SoC Encounter Place and Route, Mentor Graphics Olympus-SoC Place and Route, Avago UE schematic/art editors, RTL design and functional verification test benches, Synopsys dc_shell synthesis, Synopsys Primetime (pt_shell) timing with SDF/DSPF annotation, Synopsys VCS, Verdi, Avago CPR place and route, Synopsys Formality formal verification, Avago test insertion and Avago TRC (TetraMax), clock insertion, power management, Avago Electromigration Analysis and Timing Closure using SPICE. DFT techniques: BIST, JTAG, Parallel and Serial Scan. IP design (Serializer/Deserializer AKA High-Speed Transceiver AKA SerDes), IP delivery and IP integration (SerDes, PLL/DLL, RAM, Pads, Link-Layer Emulators, TAP, etc). Strong drive to design productivity enhancement systems. PC: Powerpoint, Word, Excel, Outlook, Visio.Specialties: SoC Encounter, Olympus-SoC Place and Route, dc_shell, pt_shell, Unified Editor, ASIC physical design, bsh, Ruby, artwork editors, rtl design, rtl verification, test circuity insertion, data delivery, ethernet IEEE 802.3ap, ethernet IEEE 80.23 ap, functional verufication, hardware design, IP, KSH, linux, microsoft excel, microsoft outlook, microsoft powerpoint, microsoft word, circuit routers, shell scripting, software architecture, SQL, TCL, UNIX, LINUX, verilog, visio,