Yield Excellence Engineer
CurrentDeveloping as a FEOL Yield Excellence Engineer at TSMC, working on defect reduction on 4/5nm processes.1. Utilized advanced techniques (SEM, EDX, TEM, CDSEM) across multiple integrated segmentation layers to identify defect root causes, mitigate yield impact, and anticipate potential risks to wafer integrity2. Established and optimized Broadband Plasma (BBP) recipes, effectively capturing and addressing key defects within the layer to enhance manufacturing efficiency and product quality3. Collaborated with the Lithography team to analyze CD data and defects, defining focus and energy process windows for optimal manufacturing outcomes