Senior Device engineer working on FinFET performance enhancement and new product installation

Senior Process Integration Engineer

Responsible for new product introduction and ownership of multiple new products during installation and mass production. This includes process development, process optimization and ramp, yield improvement, customer presentations and problem solving.

Senior Process Integration Engineer, Malta, NY, March 2015-CurrentResponsible for yield improvement, development of optimized processes, systematic sourcing of critical issues SPC, and implementation of process fixes in 300mm semiconductor wafer fabrication. This includes new product installation, process optimization and ramp, yield improvement, customer presentations and problem solving.-Key Accomplishments:• Developed multiple cleans related continuous improvement plans for defect improvement.• Implemented usage of etch buffer station for processed wafers to resolve defect excursion issue.• Implemented etch within wafer uniformity improvement to improve sigma by 30%.• Implemented improved epitaxial growth process enhancement to decrease defects, enhancing yield by 5%.• Implemented robust epitaxial growth process control techniques to balance device performance and sort yield.

Responsible for epitaxial growth module inline defect detection, defect baseline reduction and excursion control for yield enhancement. This includes daily monitoring of over 300 SPC charts for defect variations and leading task forces to drive down defect baseline and excursions to obtain optimized processing parameters for minimal defects. Other responsibilities include training process technicians on a regular basis for accurate defect classification and maintaining of the defect catalog and defect quiz.• Expertise in process and tool related defects caused during manufacturing.• Expertise in tool related defect issues in semiconductor manufacturing.• Implementation of process enhancement for 90% reduction in wafer breakage for line yield improvement. • Lead for defect limited yield improvement task force for 2 years.

Key projects worked on:• Computational Modeling of Thermal Stress Development in Silicon Single Crystals. • Computational Modeling of Indentation Analysis of Transversely Isotropic Materials.• Analysis of Residual Stress Using Instrumented Indentation.

Teaching experience for five semesters: Worked as a teaching assistant for the subjects: (i) Strength of materials, (ii) Thermodynamics of solids, (iii) Electronic materials (iv) Chemical thermodynamics.

Accumulative roll-bonding is used to synthesize ultra-fine grained aluminum and aluminum-copper plates with excellent mechanical properties at high temperatures. The properties and microstructure of the material are studied using SEM, TEM and EDX. Extensive grain refinement as well as excellent mechanical properties of the synthesized materials was observed.

Worked on a platform requiring software programming using PERL.

GaAs IC’s are fabricated using MOCVD, the defects occurring during the synthesis and processing are studied and the causes for these defects are analyzed. Scanning electron microscopy is used to characterize defects and procedures to reduce defect occurrence are suggested. The analysis and suggested procedures lead to achievement of lower defect levels in the material.