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Tamara Stuart Email & Phone Number

Chief of Staff, Director of Engineering Operations, Chipset Ingredients Team at Intel Corporation
Location: Chandler, Arizona, United States 10 work roles 3 schools
1 work email found @intel.com LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

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Current company
Role
Chief of Staff, Director of Engineering Operations, Chipset Ingredients Team
Location
Chandler, Arizona, United States
Company size

Who is Tamara Stuart? Overview

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Tamara Stuart is listed as Chief of Staff, Director of Engineering Operations, Chipset Ingredients Team at Intel Corporation, a with 10 employees, based in Chandler, Arizona, United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Tamara Stuart.

Tamara Stuart previously worked as Director of Operations, IP Engineering Group at Intel Corporation and Head of Global Operations, Mixed Signal IP Group at Intel Corporation. Tamara Stuart holds Mse, Electrical Engineering - Communication Systems from Arizona State University.

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tstuart@intel.com
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Profile bio

About Tamara Stuart

I combine engineering know how with business acumen to create order out of chaos for my organization. Using a disciplined approach and organizational abilities, I drive teams to deliver results and delight customers. I am most known for:- Managing multi-million dollar global budgets, customer and partner relationships, and driving organizational initiatives- Strategic vision, business, and technical acumen to achieve business goals- Being the "swiss army knife" for the team and division with the ability to deliver results regardless of project or assignmentAt work I am passionate about people development, leadership principles and life long learning. Outside of work I am also passionate about travel, photography and my family.

Listed skills include Semiconductors, Analog Circuit Design, Ic, Soc, and 26 others.

Current workplace

Tamara Stuart's current company

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Intel Corporation
Intel Corporation
Chief of Staff, Director of Engineering Operations, Chipset Ingredients Team
(408) 765-8080
Website
Employees
10
AeroLeads page
10 roles

Tamara Stuart work experience

A career timeline built from the work history available for this profile.

Chief Of Staff, Director Of Engineering Operations, Chipset Ingredients Team

Current

Santa Clara, California, Us

Collaborative leader and mentor responsible for budget planning and operations for the team. Partner with operations, HR and finance on budget and headcount management, workforce planning activities, organizational programs, culture, and organizational health. Partner with technical leads on indicator packages, Objectives and Key Results (OKRs), department meetings, award nominations and recognition. Coach and mentor presenters to improve effectiveness of presentations. Centralized US Intern Program owner for Chipset Solution Group.

Oct 2021 - Present

Director Of Operations, Ip Engineering Group

Santa Clara, California, Us

Leader of the newly created centralized business and engineering global operations team supporting a large hard and soft IP design organization. Team charter includes high quality budget and resource forecast, organizational infrastructure, operational indicators, variance analysis, business continuity planning, hiring, org health initiatives, engineering computer resource allocations and forecasting, software licensing, contract supplier engagements and other initiatives to ensure the organization operates smoothly and stays within budget target.Key Highlights Include:- Combined three large organization operations into a new centralized team which its own character, operating model, ramp plans and hired to target.- Lead IPG through their large scale reorganization efforts which required all new finance and organizational hierarchies, budget separations and people movements while maintaining data integrity and traceability.- Streamlined resource planning, hiring approvals, and recognition processes to enable faster turn around and lower support overhead.- Implemented new automated operational indicators for hiring, headcount and budget tracking.- Started the engineering operations team which focused on optimizing disk space and Qslot allocations, asset migration and other efficiency initiatives that delivered millions of dollars in savings.- Earned Team Excellence and Division Recognition Awards for reorganization and stabilization work.

Jul 2020 - Oct 2021

Head Of Global Operations, Mixed Signal Ip Group

Santa Clara, California, Us

Leader of a global centralized business operations and automation team supporting a large global, hard IP design organization. Team charter includes high quality resource forecast, what-if assessments, OpEx and capital budget tracking, variance analysis, business continuity planning, data integrity, hiring approvals, purchase order tracking, and contract supplier quality initiatives to ensure the organization stays within budget target. Overall division was combined with other divisions to form IP Engineering Group in mid 2020.Key Highlights Include:- Managed the operations integration for new teams joining MIG as well as executed organizational updates and actions - Defined and implemented IP end of life process- Set org. direction and initiatives, rebalanced assignments to cover gaps, and identified growth opportunities for team members

Oct 2019 - Jul 2020

Asia-Pacific Customer Application Engineering Team Manager, Mixed Signal Ip Group

Santa Clara, California, Us

Interim manager brought on to stabilize and expand a small customer application engineering team responsible for enabling timely integration of IP and resolving customer technical support issues. During my tenure I nearly doubled the size of the team, increased their scope from 2 to 4 IP domains and improved their customer feedback results.

Aug 2018 - Oct 2019

Strategic Solution Architect, Industrial And Energy Solution Division, Iot Group

Santa Clara, California, Us

- System Solution roadmap owner coordinating with product line managers and horizontal platform owners to deliver the division's first 5 year strategic solution roadmap and 3 year sales roadmap- Pilot/Proof of Concept process creator establishing a new process to the division to grade and approve requests. Resulted in enabling management to approve and execute on only the highest ROI projects.- Business development owner for a connected logistics tag application resulting in large design wins.

Oct 2017 - Jul 2018

Accelerated Leadership Program Associate (Alp)

Santa Clara, California, Us

The Accelerated Leadership Program (ALP) is a post-MBA leadership rotation program designed to develop experienced professionals into the next generation of Intel’s leaders. With the mentorship of influential senior leaders, ALP associates navigate through a series of challenging, vastly diverse, high-visibility assignments that span the entire company.Rotation 1: Strategic Lead for Secure Payments and Transactions, Retail Solutions Division, IoT Group- Product marketer for Intel’s Data Protection Technology for Transactions product responsible for creating marketing collateral including sales tools and presentations, infographics, and industry articles. Owner of accelerating end customer relationships and engagement.- Strategic lead responsible for investigating potential growth opportunities including collaborations and partnerships related to payments. Worked with Intel legal on cross-company collaboration agreements and earned a Division Recognition Award for this work. Partnered with Intel Capital to execute a Future of Payments Intel Technology DayRotation 2: Strategic Engagement Manager, Industrial and Energy Solutions Division (IESD) Commercial Support, IoT Group- Partnered with sales account owners to own the strategic relationship for IESD with key OEMs leading to multi million dollar revenue design wins. Earned a Division Recognition Award (DRA).- Developed and implemented the IESD strategic account plans, business collaboration agreements, SOWs and demo strategies across multiple accounts to strengthen and accelerate market collaboration activities.- Owned articulating account vision and strategy to external teams and senior leaders within IOTG.

Jul 2016 - Sep 2017

Primitive Collateral Team Manager, Mixed Signal Ip Group

Santa Clara, California, Us

Interim manager of a small team responsible for supporting primitive and process collateral for a 1000+ designers across Intel. Responsible for employee development and strengthening the team’s relationship with partners and the program management organization. Also was the division level representative to IPG centralized hiring steering committee responsible for defining hiring processes and facilitated the set-up of the centralized intern hiring process.

Dec 2015 - Jul 2016

Operations Manager, High Speed Serial Io

Santa Clara, California, Us

Owner of organization's multi-million dollar budget, resource modeling and forecasting, headcount tracking, and organizational process improvements to enable the organization to run in a predictable, stable and successful manner. Responsible for organizational communications, gap analysis, impact assessments and action plans during times of transition. Well versed in IP roadmap definition, planning and development cycle through post-silicon validation. Key Highlights Include:- Establishing improvement initiatives including technical work groups, lean six sigma projects, and culture of discipline.- Streamlined resource planning and recognition processes to enable faster turn around and lower support overhead.- Established and maintain external communication packets to partners and senior management. - Site Start-up Owner responsible for the creation of a new team at a new site and establishing relationships with the site leadership. - IP Lead responsible for establishing a strong and positive relationship with the new customer for the team, defining and meeting customer expectations and requirements, negotiating delivery schedules, and defining release content and requirements.

Sep 2012 - Jan 2016

Analog Design Engineer

Santa Clara, California, Us

Template and analog building block designer and owner of 10+ design collateral libraries supporting 8+ IP design teams and 20+ products on 4 process technology nodes for chipset and system on a chip (SoC) development. Extensive use of industry and in house simulation and layout tools for circuit simulation and layout verification.Lead virtual team of 10 engineers and mask designers to design copy exact, Intel wide analog building blocks and template cells on 14nm to enable product and IP designs. Responsibilities included pathfinding, cell specification and definition, international resource coordination, defining release methodologies and schedules, overseeing cell development and verification, quality control and design of debug experiments.

Jul 2006 - Sep 2012

Mission Operations And Public Affairs Internship

Washington, Dc, Us

EarthKAM is a NASA educational outreach program that enables students, teachers, and the public to learn about Earth from the unique perspective of space via the International Space station. This program is located on UCSD's campus and provides internships to students. Internship included:Mission Chief 6/05 to 11/05 responsible for overseeing all mission operations, handling all communication with NASA's Johnson Space Center, team coordination and training, problem solving and conflict resolution.Team Leader for Public Affairs/Outreach 7/04 to 9/05 (member of team since 9/03) responsible for overseeing, managing and motivating team members, training, coordinating with superiors, coordinating task management and enhancing the outreach program. Increased program participation by over 100%.

Sep 2003 - Nov 2005
Team & coworkers

Colleagues at Intel Corporation

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3 education records

Tamara Stuart education

Mse, Electrical Engineering - Communication Systems

Arizona State University

Mba

W. P. Carey School Of Business – Arizona State University

Bsee, Electrical Engineering - Circuits And Systems

Uc San Diego
FAQ

Frequently asked questions about Tamara Stuart

Quick answers generated from the profile data available on this page.

What company does Tamara Stuart work for?

Tamara Stuart works for Intel Corporation.

What is Tamara Stuart's role at Intel Corporation?

Tamara Stuart is listed as Chief of Staff, Director of Engineering Operations, Chipset Ingredients Team at Intel Corporation.

What is Tamara Stuart's email address?

AeroLeads has found 1 work email signal at @intel.com for Tamara Stuart at Intel Corporation.

Where is Tamara Stuart based?

Tamara Stuart is based in Chandler, Arizona, United States while working with Intel Corporation.

What companies has Tamara Stuart worked for?

Tamara Stuart has worked for Intel Corporation and Iss Earthkam.

Who are Tamara Stuart's colleagues at Intel Corporation?

Tamara Stuart's colleagues at Intel Corporation include John Rubio, Janis Calhoun, Agus Hendro, Penney Armstrong, and Anantha Padamanabha.

How can I contact Tamara Stuart?

You can use AeroLeads to view verified contact signals for Tamara Stuart at Intel Corporation, including work email, phone, and LinkedIn data when available.

What schools did Tamara Stuart attend?

Tamara Stuart holds Mse, Electrical Engineering - Communication Systems from Arizona State University.

What skills is Tamara Stuart known for?

Tamara Stuart is listed with skills including Semiconductors, Analog Circuit Design, Ic, Soc, Mixed Signal, Simulations, Sensors, and Microprocessors.

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