Senior Ic Design Engineer
Current• Responsible for the overall implementation of the design for testability (DFT) scan of a chip. Tasks include editing RTL, planning scan IO, running Spyglass DFT, performing scan insertion, etc. Collaborates with others for ATPG, timing closure, and signoff.• Verifying SoC ASIC design for DFT scan for SAF and TDF modes across RTL, prelayout, and postlayout netlists with both UPF and SDF by running the digital simulation.• Researching DFT scan methodology and collaborating with the DFT and APR backend teams to improve workflow and SoC PPA quality. Guided engineers on topics of DFT scan. • Partitioning an SoC ASIC design into multiple FPGAs for firmware development and testing while ensuring their functionality is similar to the ASIC design.
