DV related resource/platform/strategy planning. SSD based Key-Value Storage System architect and DeepSSD series solution planning. In charge of the EYE BOX platform/product management for market/arch/technolgy/application, which includes the AI platform/algorithm, Distributed Storage/System/Application, Database accelleration, SSD FW/Driver， FPGA HW/FW/Driver, Operation System/Docker/VM , UI/Service, Test and System Qualification. Whole project include 5 departments inside and 2 other companies.

Project planning, supervising and resource arranging among different members in different sites which includes Shanghai/Chengdu and so on. Technical trending studying. Team motivation and NCG training for better understanding start-up company.Plan for whole frontend flow, tool, develop and integration strategy. UVM/C/C++/Matlab based IP DV environment training and handle part of the core algorithm IP DV work. Hybrid SOC DV enviornment development which includes IP/CPU/Functional/Low Power/FPGA/BIST/EMU and PG-netlist. Project DV test planning and DV sign off review planning. Part of the FW test/development work involved

IP DV environment build , case create, regression and coverage collection. Create the SOC DV environment which includes the SUB-IP/Peripheral/Firmware/Low-power/Post-Sim/PG-Post-Sim, provide the SOC DV environment for all members and create the low power firmware code. Write/update SOC TOP UPF according to the design requirement.

SOC Verification

IP Verification, C/System C/C++ tools/BFM developments, UVM reusable test environment developments, FullChip Verification. TCL/Shell/Perl Script coding, Makefile/Testflow building

Co-work with Marvell guys for SOC integration, create test bench environment and test cases for IP verification. Introduce the data path and architecture of the IP in over two months. Deliver the IP and test environment to Marvell for Sub-system level alone. Tests include all data path, work modes and new ARM control logic instead of the original MCU51 in the IP. Take another one-week short trip to Bangalore(India) for the whole system integration verification. Port all typical use mode cases to the real fullchip verification system, deliver a steady typical test/work flow for the sub-IP work correctly in the SOC system. All tough work was done alone within a short time and high pressure.

Several IPs Verification in 3D display card Dept., Code Integration from working depot to release depot for whole display project, Soc Build Lead