• Worked on RTL and microarchitecture for crossbar across chipset.• Executed Synthesis, timing, and LINT check for the IP.

• Leading RTL design and microarchitecture on SMMU (Memory management) IP features. Responsible for adding multiple features, timely delivery of the design to SOC and DV, root cause issues, implementing ECO (netlist correction of issues), silicon debugs, understanding and correcting the design post timing feedback.• Mentored new peers and strengthened their grasp on the IP and supervised timely project submission.• Collaborating with peers to solve complex issues for the team.• Snapdragon 855, 7nm: Enhanced SMMU design to bump up the frequency of operation by 25%. Compiled specification for SMMU after multiple discussions with architect and dependent IPs. Enhancing performance features to assist in visualizing SMMUs traffic in silicon and in debug.• SM6250: Debugged a silicon hang and suggested a workaround for a completely new IP in a week.• Snapdragon 780g, 5nm: Oversaw a team for freezing the SMMU configuration and CDC/LINT/SYNTH clean design and timely delivery. Addressed and monitored closely to resolve issues seen in design before the project deadline and corresponded with the SOC and IP DV team. Collaborated with the SOC power team to finalize on the power protocol of SMMU from the system perspective.• SM8550/SDX75: Resolved an issue in SMMU silicon using scan dump register data and suggested a fix forthe same. Enhanced test-bus feature for better debugs.• Contributed to developing a python script to efficient RTL generation by 20%.• Technical Publication: Co-author of SMMU Performance and Area optimizations across Tiers for QBUZZ (Qualcomm technical extravaganza). Executed a design change to scale up the supported frequency on a block in SMMU by 25%.

I have been working in the Qualcomm since Oct, 2017. It has been a very learning experience so far for both technical and personality traits. About my role, i am a Design engineer working on an IP (MMU) and have delivered multiple projects and also had hands on on many design changes.Working as a design engineer in VLSI is a demanding task which never ends even if the chip is in the market because one is involved into debugs and support. I had experience on this front as well.

profile includes :Front End (RTL DESIGN).

my profile at NXP was back end circuit designer. I joined NXP as an intern and worked on a project on 16 finfet, based on estimating aging phenomenon in cmos. During the internship period had good exposure to circuit simulations and analysis and shell scripting and many non-technical learnings.