Building Valeo's HIL Cloud

FPGA Expert who provides consultations and trainings to several product lines.

• Turnkey Hardware In then Loop 'HIL' solution provider and architect, used for SW Validation• Recruit and grow my engineering teams (~25) and boost the technical know-how within • Manage parallel projects, resource planning and enhancing customer satisfaction• Successfully deliver a HIL test bench to 450+ projects at 6 R&D sites and 3 production sites

Design, develop and Implement state-of-the-art test benches for automotive hardware-in-loop (HIL) validation. Test benches include HD video streams, high-performance ultrasonic sensors simulation, Flexray and CAN bus communication. I design system PCBs, FPGA IPs in VHDL/Verilog, code firmware in C and integrate with a Java Test-Automation Environment. I lead a team of 10 engineers to develop and customize test-benches for tier-1 automotive customers; 20+ projects at more than 3 sites around the globe. This testbench validates ECUs for automatic self-parking cars, Laser radars, Video surround views and many driver assistance features.

I have participated in the designing and implementing several decimal floating-point (DFP) arithmetic IP cores comforting the IEEE 754-2008 standard. My responsibilities at SilMinds include agile project management, system level design, data path optimization, static timing analysis, FPGA tailoring, HDL coding and writing automation scripts for EDA tools. During this period, several papers were published (listed below). I hold pending patents at the USPTO of several designs.Apart from the IP cores, I was responsible to design and lead the implementation of a vector DFP co-processor; this project included many architectural design, multiple clock domains, data-path optimization, designing op-codes, test banches, low-level drivers, mini c-assembler using macro dispatchers, use cases and patenting many of those.I have been outsourced for 4 months to Varkon Semiconductors. There, I built an on-chip testing environment for their IP communication core. Memory controlling, high bandwidth throughput and hardware testing were among my duties. Microblaze soft processor is configured and programmed to accomplish the task.

SysDSoft is acquired by Intel, now called Intel Mobile Communications. I managed the hardware-in-loop validation for our wireless 802.11 a/b/g/q chips.