SoC Performance Architect, Performance Technical lead for AMD Instinct MI Accelerators.Led the Team developing SoC Models for End-to-End Performance Projections, Bottleneck Analysis, Design Trade-offs and Performance Attainment

* Led the Memory-System Performance team evaluating various Performance/Power/Area (PPA) design trade-offs across multiple SOCs.* Innovation and design enhancements spanning Load-Store, Prefetcher, MMU, Caches, Interconnect and Memory Controllers* Built partnerships with industry and academia through collaboration on multiple research projects

* Technical Lead of the core performance team evaluating a next-generation CPU.* Owner of the core Load-Store, MMU and cache performance models, and responsible for performance studies and correlation of features encompassing these blocks

* Performance modeling and analysis of Qualcomm's Hexagon DSP core.

* Development of functional, timing and power models of an out-of-order PowerPC embedded core.