Space Defense Systems :Survivability, Sensing and Targeting:Internal R&D

Contract work teaching Digital Fundamentals, Analog, and FPGA development to under grads and graduates with class sizes up to 66 students. www.ynnu.edu.cn

CMTS product design. PCB 28 Layer, 300W, multi- 10GBaseKR, multi-40GBaseKR, 500MHz ADCs DDR4....

o Laser Induced Breakdown spectroscopy (LIBs)- design argon flush control sub-system for enabling LIBs measurement of carbon.o Board and FPGA designer for XRF, LIBs, and RAMAN hand held instruments.o Main duties centered on XRAY digital pulse processor (DPP) design & control systems in ALTERA based FPGA devices for low noise, low power XRAY applications. Implemented in verilog, vhdl, and .tcl scripting.o Consultant for PI, SI, digital design, analog design, FPGA design, schematic entry, board stackup, layout, and enforcing considerations for DFM, DFT, EMC, and UL.o Low cost budgetary tools used for SI simulation ( Hyperlynx ) using 3D models produced in HFSS.o Secondary duties around Raman and IR spectroscopy. Other duties, design custom cores for serial IF : SPI, UART, I2C, precision stepper motor control, packet parsing, ADC and DAC control. Created a custom FPGA DV environment. Wrote scripts (native tool script language) in .tcl for ModelSim and Quartus.. o Write functional and detailed specifications.o Worked with junior members of the hw development team to review work and gave feedback to improve DFM, DFT, DFA, testability and quality. Group review driven and documented through SMARTSHEETS.o Write white papers to enhance product deficiencies, and instill innovation in future products. Invent new functions and methods for improving product efficiency. o FPGAs : Altera CYCLONE IV family. FPGA design for XL5 product, Converting Xilinx Spartan to Altera in mixed VHDL and Verilog with new designs being verilog centric. Implement an FPGA DV environment to support several engineers using source control, tcl scripting, Quartus, ModelSim.Download file .... "Life of an Impulse.mp4"An animated presentation of XRF pulse shape processingLink :https://app.box.com/s/z312406v8sgcxcurx12g1x8zn8w0tmwt

Hardware designer on10x10GE line card. Hardware support for a 40x1G line card. Write board functional and hardware specifications. Feasibility on power distribution for 1200watt system. Utilized 2x EzChip network processors and Dune switch fabric chips in a 20 slot system. Signal integrity and board geometry definitions for 6.25/12 Gbps links. Raw back plane connection bandwidth 300Gbps. Raw 6Tbps backplane bandwidth.-200Gbps modules, 3D/2D Hi-speed geometry modeling,47” 6.25Gbps channels w/Amphenol Xcede connectors,Agere SERDES, Power Integrity, 0.9V@40A to 48V@10A. 1G, 10G, and 40G sfp,XFP line interfaces. 12Gbps channel designs for future proof. 38 layer backplane, 24 layer line card designs utilizing Dual Backplane ASiCs, Dual EzChip Network Processors, Dune/Broadcom Fabric Processors, DDR3-300, SRAMs, several 100MHz busses. I/F include XAUI, RGMII, PCI-e, Interlaken 6.25Gb, XFI, DDR3, & QDRII. -100Gbps modules On new projects Virtex2 pro, Virtex 4 designs “Services Switching Unit” FPGA, dual MAC, QDRII-200, Pci-32,Pci-x, Pci-e, x4 Aurora 3.125Gbps 8B10B links, NSE controller, StRR dual level arbitration to support 2K ingress flows. Focus bus, 200Mhz proprietary ddr bus & proprietary protocols. Error detection using DIP and CRC. Error detection and correction. White paper to determine in band error detection fields for serial links. -Revive the Dense Virtual Routed Technology from Crescent Networks. 22 Layer processor board designs. Virtex II Pro FPGA design including 200Mhz DDR, PCI-X, NPU I/F, PMC I/F, Dual Gbit GEMACs. Close any “open board” issues on designs not completed at start-up closure (included respins).Paper: Hashing Algorithms For Network Processor Load Balancing https://app.box.com/s/8dg2sw3d19120d3n4fhx73eehl2mtetb

Consulting and design on Advanced Telecommunication Computer Architecture (ATCA) 2.4Ghz Dual Xeon Processor Blade consisting of one PMC card, IDE hard drive, 4 Phase Switcher, 4-Gbe ports, USB, Dual SCSI-133, 4Gbyte DDR 266, IPMC, FLASH, INTEL E7501 Chip Set. Work was mostly based in Shanghai, China.

Preliminary work to acquire funding for a new Start-up Company. Providing technical expertise in the research and support of a new ASIC. Plan for proof of concept in "Xilinx Virtex II Pro"​ FPGAs to show customers/investors the feasibility of the product. Required...- IP Core evaluations, Planning for the design of custom IP blocks- Writing specifications- Research/study of protocols SIP, SDP, RTP, MGCP, H.323- Plan for IP support blocks for IBM's PLB and OPB bus architectures- IPsec functions for encryption/decryption core evaluation- Implementation of four IBM '405 processor cores with embedded SDRAM- Evaluating new pieces of XILINX ISE tool suite- Creating Parts lists for an evaluation platform including DDR SDRAM, QDR SDRAM, PCI interfaces, - PL3/CSIX interfaces, CAM search engine, PCI-X & GigE interfaceWork consisted of a team including an Architect, Hardware Engineer (myself), ASIC engineer, 2 Software Engineers, and a Marketing Specialist.

Contributed to the development of a Dense Virtual Routing Switch. This QoS sensitive dense virtual router can replace up to 2K Cisco routers. The IP was sold to Marconi/Ericsson. Aided in support of the sale of the IP, was one of the last 20 employees out of 158. A solid product.-Primary Roles-Bring from conception to manufacturing, a variety of SONET line cards for the Dense Virtual Routed Switching product. Cards included ...- Dual Port OC12 ATM card with APS- Quad Port OC3 ATM card with APS- Hex Port DS3/E3 ATM card with 12 port varianto Design Oc12/Oc3/Ds3 Atm cards for Dense Virtual Routed Networking Switch. Included logic design of 300K gate FPGAs, Cpld, Signal Integrity work on 800 Mhz Rambus layout, Analog design on hotswap and power control, Telecom interfaces. Boards included Network processors (up to 4), RAM, SRAM, PCI Bridges, peripheral chips. Xilinx FPGAs. Spice Simulation. o Brought boards through production, supported software. o Some design verification on FPGAs. o IO standards: PECL, LVDS, Rambus signalling, and RAM interfaces at clock rates of 100,132, and 400Mhz raw board clock rate.Individual-Group participant Roles o Consult on high speed design issues including analysis and re-layout/clean-up of a faulty (400Mhz clocked) 800Mhz RAMBUS design. o Logic Design implemented -XCV200E , XCV300E devices and logic design for ingress and egress paths on various system cards - 100Mhz FPGA designs, DLL functions, packet inspection, storage, SDRAM controller, SRAM controller, table look-ups, header manipulation and compression, parity checking, assembly, disassembly, for ATM, SONET and Frame Relay. Spartan FPGA for APS functionality, -Xilinx CPLD for control bus functionality and hot swap controlo Support Software for debug of system boards during software development. o Design analog telecom interfaces, PCI interfaces, o Tools : Spice Simulation NcSim, NcVerilog, ModelSim, Synplicity, DxDesigner,Agile, Allegro

o Design QoS Data communication controller card for Computer Telephony Integration Product. o Consult on signal integrity issues for high speed design, various 100K/30K gate Fpga logic design, CPLDs, analog design. Created proprietary Ring controller 100mtr at 200Mbps. o Analog phone trunk designs, gyrators, MVIP Bus, TDM, Design Hot Swap control on cards, oSwitching supply design. o Work with Design Verification people for FPGAs. o Support engineers in schematic capture. FPGAs included Altera & Orca. Lattice CPLDs, Spice simulations. o features : CTI equipment supported teleconferencing, email server, voice mail server, enet switch, T1,DSL,Trunk lines, and 16 to 40 phone lines in a VCR type rack mountable box.

Evaluate optical/serial/parallel high speed serial links (>1Gbps) for 50Gbps switch. CDV and Class Queuing scheme analysis to minimize ASIC IO pins/memory BW/power. Investigate concentration and group concentration techniques, multi-cast manipulation/trade-offs. Backplane Connector evaluation. Attend high speed digital interconnect workshop in Santa Fe. Evaluate communications analyzers for TDR, FFT, and differential apps. Evaluate backplane vendors, Backplane lay-ups, signal integrity, White paper on SPICE skin effect modeling, Backplane schemes for ring, optical, juncture, star. 2D modeling software. Design of ATM uplink card for a 12 port Ethernet to ATM switch.

Engineering role on various products....-acquiring regulatory agency approvals -writing specs-scheduling for system tests. -bringing boards through layout/debug/dvt/mfg-training manufacturing and foreign facilities. -product lead roles on two products. _________________________________________________-Low Cost Alpha VME: Design support for Low Cost Alpha 21068 VME module.-PC ISA router Card: Pick up design mid-project from Puerto Rico plant closure and bring to production. -Feasibility study for hot swappable VME bus backplane to be used for T1/Voice platform.-Hardware lead and design for 68302 based TURBOchannel Sync/Async communication module for DECstation 5000. EIA I/O standard (ie RS422, V35). Train DEC Annecy, France personnel.-Lead role for design of two data cipher processor modules. Design a uVAX based VAX-BI module and lead development of a 68K based VAX module. Modules encrypt/decrypt data using DES algorithm.-Feasibility study for design of a high speed transmit DMA unit for a 40-80 Mbyte/s Bus. Design of DMA circuitry, byte aligner, parity control, and bus control logic. Interface to AMD29000 20MIP uPC. Analog backplane simulation using SPICE. -Designed and developed uVAX based CPU card for fiber optic communication gateway (AT&T customer). Trained AT&T customers & field service.-Evaluate chip sets, build and design prototype T1-CSU to attach to DSB32 communication product. Presented to marketing

Design of a daisy wheel printer analog board. Stepper motor interface, 8085 uPC, 3x 8741 slave uPC. TEMPEST switching power supply design, active/passive filters. Government secret clearance.

Marine Systems Engineering Lab, KRL Electronics, Fire Blind, CushCraft Antenna