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I have 20+ years of experience in ASIC/SOC verification and s/w development. I have hands on experience in complete ASIC verification cycle. My industry experience covers start-up to mid-size company transformation. I have been serving the company as Individual Contributor; Team player, Leader, project manager as and when it is required. I am keen in meeting dead line using my engineering background and time management skill.Experience in making Test plan/Test cases, Test Bench development, Debugging, coverage report, handling regression of block level as well as fullchip level. Gatelevel simulation. Post Silicon validation and debugging.Expertise in System Verilog, UVM based Test bench preparation.
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Principal EngineerMarvell TechnologyCupertino, Ca, Us -
Principal EngineerMarvell Technology Mar 2015 - PresentSanta Clara, Ca, UsHandling a complex block of current project. Responsible for whole verification cycle for the block. Test bench for the bock is developed using SV and UVM. Block is signed off after producing coverage and regression report. Also worked on sub-system level for verifying Tensilica DSP (18) related functionalities. -
Principal Engineer -Ic DesignBroadcom Oct 2014 - Mar 2015Palo Alto, California, UsPrepared Testplan for SMMU (System Memory Management Unit) Developed and maintained Test bench for SMMU using SV and UVM. Produced initial coverage report. -
PmtsCortina Systems Jul 2011 - Oct 2014Sunnyvale, Ca, UsFunctional verification of Scheduler, Buffer Management, DDR controller, and USB3.0 IP. to prepare and review test plan to prepare Test bench for complex block using System Verilog with UVM concept.to handle regression with functional and code coverage closure.to achieve 100% line coverage and > 85% expression coverage.Evaluated cadence tools for accelerating verification process.Defined work for India team and prepared work-status from the meeting. -
Technical LeaderCortina Systems Jan 2004 - Jul 2011Sunnyvale, Ca, Us* Took interviews for expanding the company in design, verification and software side.* Managed complex block (Scheduler, Buffer manager, DDR controller) as well as fullchip verification cycle using Verilog and Vera. - Prepared Estimation of the man power and dead line of the project - Involved in defining specification for the chip. - Prepared as well as reviewed Test plan (various blocks as well as fullchip) - Lead the verification team. - Handled regression with functional and code coverage. - Successfully managed to verify SoC on Palladium before bring-up. - Worked on FPGA setup and bring-up activity. - Worked on few customer queries after taping out the chip.* Achieved 100% line and expression coverage at block level.* Evaluated EDI tools for the team.* Setup complete verification environment for Traffic chip (Reassembly and QDR-II memory controller) in System C -
Tech ChampionEinfochips Aug 1997 - Jan 2004San Jose, California, Us-Built/Managed/Led team with complete service cycle including understand the requirement, define the specification, architect the platform, design, develop, test and deliver the project on estimated time.-Built sound relation with the client by providing quality deliverable s. -
Executive R&DSecure Meters Limited 1994 - 1997Developed Energy watch system (SCADA system) using OOP concept.Developed Billing/Routing/Reporting System using Hand Held Unit (HHU).Evaluated HHU suitable to electricity board.Gave presentation and training to electricity boards for usage of embedded S/W using HHU in their billing process.
Tejas Talati Skills
Tejas Talati Education Details
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Birla Institute Of Technology And Science, PilaniSystems And Information Systems -
Gujarat UniversityComputer Engineering
Frequently Asked Questions about Tejas Talati
What company does Tejas Talati work for?
Tejas Talati works for Marvell Technology
What is Tejas Talati's role at the current company?
Tejas Talati's current role is Principal Engineer.
What is Tejas Talati's email address?
Tejas Talati's email address is te****@****hoo.com
What is Tejas Talati's direct phone number?
Tejas Talati's direct phone number is +140894*****
What schools did Tejas Talati attend?
Tejas Talati attended Birla Institute Of Technology And Science, Pilani, Gujarat University.
What are some of Tejas Talati's interests?
Tejas Talati has interest in Science And Technology, Education, Environment.
What skills is Tejas Talati known for?
Tejas Talati has skills like Functional Verification, Verilog, Systemverilog, Asic, Soc, Vlsi, Debugging, Fpga, Embedded Systems, Uvm, Vera, Systemc.
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