Thane Larson Email & Phone Number

Santa Clara, California, Us

Responsible for Architecting and Validating Servers, influencing chip directions, assisting development of platforms and Validating the systems

Houston, Texas, Us

Lead computer server architect for Cost-Focused, Dual CPU Integrity Server (2007 to 2010) Hewlett-Packard. I defined the entire architecture of this generation of HP's dual-socket Integrity server. I coordinated the technical solution with a team of twelve engineers and worked with Asian contract design houses and manufacturers for bringing the product to market.Test Lead for Highly scalable x86 (2009 to 2010) Hewlett-Packard. I lead, coordinated, and tracked the overall test verification of an eight-socket, multi-processor x86 design.RAS Architect for all entry-level PA and IPF servers (2002 to 2010) Hewlett-Packard. Since 2002 I was a RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) architect. I defined RAS requirements for both chipset and server designs. I negotiated new features with partner teams through careful business and marketing analysis. I created new procedures for development teams. One result is that the 2006 products are three times as reliable as the previous generation with twice the performance. In addition, I regularly presented product features to customers and was brought in for technical support in sales situations. Manageability Architect (1999-2001) for the first HP blade systems. Represented HP in the PICMG 3.0, RASM subcommittee which defined the manageability standards for telecommunication, NEBS-compliant servers.Give numerous customer presentations and have over 35 US patents.

Houston, Texas, Us

Created and verified several processor modules used in the HP, PA-RISC 9000 line of servers. I have been through the entire design cycle: investigation, proposition, negotiation, scheduling, execution, verification, and support on these modules. I have partnered with marketing, manufacturing, and other engineering disciplines. For the design cycle, I have created schematics, laid out the PCB, run signal integrity simulations, and released the design for manufacturing. I have also given seminars and talks to peers at HP as well as contract manufacturers. In addition, ran experiments in high energy neutron bombardment of memory & processor components.

Oakland, California, Us

Advised on the purchase and taught how to use specialty accounting and generic computer programs for IBM and Macintosh platforms. Advised on purchase, installed, and repaired computer equipment. Wrote custom accounting programs including a database system.Highly proficient in Linux, UNIX, Windows, Perl, AWK, HTML, BASIC, PASCAL, FORTRAN, and 808x assembly. Familiar with C, C++, PDP-11, and VAX-11 assembly languages.Highly proficient in Web design, Mentor Graphics tools, Matlab, Mathematica, Spice, Corel Draw!, Word, WordPerfect, WordStar, Excel, and Lotus 123 programs. Familiar with Suprem, Magic, Autocad, RBase, Cadence board design. RESEARCH EXPERIENCEMasters and Doctoral Research

Gaithersburg, Md, Us

Research scientist, characterizing the magnetic and electrical properites of superconductors. Wrote research papers. Measured magnetic and current capabilities of superconductors. Wrote real-time data acquisition and analysis computer programs. Assisted in presentation of results. Assisted in development of low resistance electrical contacts for ceramic superconductors. Designed, machined and built cryostats and other low temperature (4 Kelvin) measuring devices that required nanovolt sensitivity, thousands ampere drive current, while immmersed in magnetic field as high as 20 Tesla.

Ph.D, Electrical Engineering

M.S, Electrical Engineering

B.S, Electrical Engineering; Electronics

Education record