Therese Kinney Email and Phone Number

Manages cluster pre-Si verification tasks including project and verification planning. Performs individual contributor work such as verification requirements definition, SV UVM coding, simulations, and debug. Experience with CXL IDE, data encryption, forms of hardware security, technical reviews, and risk assessment. Works with cross-functional teams to understand usage models and ensure that these are tested in pre-Si. Works with IP providers to reconcile external and internal schedules, align development activities with resources for optimum execution. People manager; passionate about people development, mentoring, and managing roadblocks so the team can achieve project goals and have the opportunity to attain their career best. Believes in understanding the team's work and challenges by balancing technical growth and people management. Experience with RIHV (rapid integrated high velocity) for methodology and process improvement.

SSD controller fullchip verification task management and execution. Led a team of pre-Si verification engineers in defining verification requirements, building the testbench and the fullchip model of SATA and NVMe based controllers, reviewing simulation results, and debugging. Familiarity with C++, System Verilog, UVM, fullchip integration and connectivity, and data encryption algorithms.

Built digital FC model with layout parasitics/back annotation to validate performance of a DDR2 device. Used SV UVM/OVM fullchip test sequences and coverage closure. Worked with DA to implement netlisting automation to support a more efficient fullchip model build methodology. Worked with the post-Si team to convert capture vectors into preSi stimulus to ensure fully functional test tapes for first Si checkout.

Responsible for mixed-signal fullchip build/methodology and other tools/methodology evaluations prior to implementation/use on design projects. Worked on a Specman-based automated test mode checker. Defined guidelines for analog block vhdl-modeling and equivalence for analog designers to generate their own models and minimize issues at fullchip integration.

Worked on High Voltage and Read Path circuits for NOR memory devices. Supported first Si characterization activities using the microprobe, oscilloscope and logic analyzer. Led an analog section in a design project. Took on the pre and post Si validation role for a NOR device and worked with a cross-functional team to complete all preSi activities on schedule, prepare for first Si, and to resolve issues seen during the first few weeks of post-Si debug.

First Si poweron/debug, product characterization, product qual, yield and manufacturing flow improvement, manufacturing support.

Taught Industrial Electronics and Basic Electronics courses.