Senior PCB Layout EngineerMar-2020 - Sep-2021Lead Cisco PCB layout projects, team leader and training new employees. 90% of these boards have 12+ layers and upto 38 layers; 5K to 20K components; 3K to 13K nets DDR4/DDR5, PCIe gen4, PAM4 interface, SGMII, USB2/USB3…etc SAS, SATA3, XAUI, XFP, SFP, SFP+, Backplane  High current density power rails, Back Drilled Technology DFA/DFT/DFM verificationLayout tools: Allegro pcb editor, Cadence Sigrity, CAM350.

Senior PCB Layout Engineer/ 3D designer – Thermal simulation designer2016 - 2020(The server SoC business of AMCC was acquired in 2017 by Ampere) Perform layout and routing studies for layout team and package team.  Place and route complex, high speed, multi-layer PKG Substrate and PCB’s including trace length adjustment, GND shielding, verification, etc. Interface with PKG Substrate/PCB layoutgineer to setup design constraints and for BGA pinmap optimization. Completed the EVT/DVT boards for X-Gene 3 and Ampere Altra 64-Bit Multi-Core Arm Processor. Provide design solutions, improvements in manufacturability and reduced time to market. Worked closely with the Mechanical team, SI team and package team to support them on some internal projects.Layout tools: Allegro pcb editor, Allegro Package designer, Cadence Sigrity (PowerSI, PowerDC), Ansys HFSS, HyperlynxSolidwork 3D, Solidwork flow simulation, Viewmate.

Senior PCB Layout Engineer/ 3D designer – Thermal simulation designer2016 - 2020(The server SoC business of AMCC was acquired in 2017 by Ampere) Perform layout and routing studies for layout team and package team.  Place and route complex, high speed, multi-layer PKG Substrate and PCB’s including trace length adjustment, GND shielding, verification, etc. Interface with PKG Substrate/PCB layoutgineer to setup design constraints and for BGA pinmap optimization. Completed the EVT/DVT boards for X-Gene 3 and Ampere Altra 64-Bit Multi-Core Arm Processor. Provide design solutions, improvements in manufacturability and reduced time to market. Worked closely with the Mechanical team, SI team and package team to support them on some internal projects.Layout tools: Allegro pcb editor, Allegro Package designer, Cadence Sigrity (PowerSI, PowerDC), Ansys HFSS, HyperlynxSolidwork 3D, Solidwork flow simulation, Viewmate.

PCB LAYOUT DESIGNER2011 - 20152011: Be trained in all specifications of PCB layout design.2013 - 2015: Lead a group 5 members in storage system layout design boards and Intel server boards.My background in PCB layout are: Structure of multi-layer (4 layer, 6 layer, 8 layer, 12 layer...). EMI/EMC problems for PCB design. Signal Integrity (impedance, length matching, shielding GND…). Skills of routing for USB, DDR3/4, Sata2/3, PCIE Gen3… Power plane cutting.