- Project leading in charge of feasibility study and SIP project execution/implementation.- Projects: SoC ModAp (LTE modem + APE, 32/28nm), modem (LTE), RF (28nm) etc....- Multi-site work, travel in India (Back-End support and SIP co-design), Sweden (platform), etc....

Physical design team management, in charge of the implementation of SoC ModAp and modem/LTE:- Floorplanning- Low power: strategies, definition, implementation and verification (feasibility/architecture, upf/cpf, power attx, ...)- Voltage drop static and dynamic- SignOff (DRC/ERC/LVS, finishing ...)- DFM : Design for manufacturingMulti-site work: India, England, Sweden, Finland ....

Definition of the SoC BackEnd technical coordination activity: - physical/analog/layout/power/floorplan expertise center - involved in project definition, planning and implementation - functional relations with CR&D (Crolles) for Kits, Librairies, and Process. - librairies/Kits management for CCD/DSA/customers - packaging / PCB team interface (CPA and customers) - technological survey for new process - analog et custom IPs interface - engineering/test interface (circuit debug, failures, yield, industrialization) - communication and reports to Project Leaders / Program Managers / technical marketing - investigations linked to projects: NBTI, IRDrop, leakage, Uncertainty/Timing… My functions and activities: - technical coordination leading: 10 Baseband (90nm / 65nm / 45nm), 2 GPS- ‘Object Leader’ : 1 chip 2006

- Responsible of Design Kit RFCMOS8 (0.18μm with RFdevices) (1y 1/2) - Involved in Design Kits development hcmos8 and hcmos8d (1y 1/2). - Responsible of DK hcmos9, 0.13μm (2y) - Responsible for Crolles 1 of Design Kits cmos090. - Developpement "from scratch", with Motorola et Philips, of the Techno Kit cmos090 (Crolles 2) for back-end aspect, - tool development to automate generation and validation of DK (Skill, perl, csh, Makefile) : covalidation of plateform, calibre flow, dummies generation automated (DKP tools)… - Responsible of P&R (Analog on top) flow development based on LayoutXL / CCAR (ICC) / Opus (ic) 5.0. Implementation of the CBANA9 65A and TO in 2003- Open Access DK migration

The Flash Analog to Digital Converter (Flash ADC) is a key element in the high speed data acquisition. It has been proved to be highly sensitive to the spatial radiation effects. Therefore, the principle of the proposed method relies on a partitioning of the Flash ADC architecture in different blocks for the purpose to identify each behavior and responses to perturbations. Then, in a second step, we develop the two complementary hardening techniques: a reconfiguration technique of the logical structure coupled with a design hardening of the individual blocks.The necessary specific work on latches and the final design of a hardened Flash ADC have lead to the realization of several test circuits in a standard technology. The simulations joined to some ground tests tends to demonstrate the hardening improvement of the proposed solutions.- 3 chips designed: DAC, 2 memory chips- test with HP83000 (industrial tester)- Teatching: 220H- 5 students projects leaded- 12 papers