Thilo Wagner Email & Phone Number

Dresden, De

Head of the "Design for Testability" Line at Europe's leading ASIC Design Service Company. Organizational, managerial and employee responsibilities. Project Management / DFT Architect / Flow Development / VLSI Enthusiast.Built the Racyics DFT team from scratch across multiple sites. My team of experienced DFT engineers ensures, that System-on-Chips for automotive, industrial and consumer applications can be tested during production and throughout their entire life cycle.

Frankfurt, Langen, De

Line manager, Project Manager and Lead Engineer of the Design for Test (DFT) team.Defining hierarchical full-chip DFT concepts for 45nm - 7nm mixed-signal ASICs up to a complexity of >500M Gates and >1000MBit SRAM for industrial and automotive.Project management and leading the DFT implementation, including definition of full-chip DFT concepts, resource planning and monitoring, risk analysis, reporting to customers and upper management and handling all communication with customers and other design groups. Leading the DFT flow implementation across different geographies including on-site trainings in China and Japan; strong scripting and flow automation skills.DFT implementation based on EDA tools from Mentor, Synopsys and Cadence:Scan/ATPG (full hierarchical, compressed), At-speed testing, MBIST, MBISR, Boundary Scan, JTAG/iJTAG, mixed signal IP testing, test mode timing constraints & STA, LINT & LEC, gatelevel simulation with SDF, timing closure support for physical implementation team, ATE bringt up support, post-silicon debugging

Frankfurt, Langen, De

Frankfurt, Langen, De

DFT lead engineer and Project Management for a 16nm optical networking ASIC with 20 physical blocks, 160MGates und 18Mbit SRAM.Managing and leading all DFT tasks from supporting the customer during RTL implementation via DFT concept definition, DFT implementation, test pattern generation & verification till successful mass production.

Jp

ASIC Design for Test (DFT) and Physical Implementation from Netlist to GDS.Participated in over 20 tape-outs down to 55nm. Top-level physical implementation for 0.11um - 55nm designs (HDTV decoder, automotive APIX converter, ..) including all steps from netlist via DFT, frame generation, place & route, physical verification, STA & timing closure to successful tape-out.Technical interface for COT customers in middle east.Project Management for several ASIC projects.

Working in the 3G mobile communications R&D team on HSDPA simulations