Thinh Tran Email & Phone Number

Fremont, California, United States

MRAM design in 40nm and 22nm. High speed, low power circuit techniques in both embedded macro and stand alone chips.

San Jose

- Technical lead in all synchronous Synch/NOBL, QDR, QDRII+, QDR4 and QDR Wide-IO SRAM design from 90nm, 65nm and 28nm from 4M to 288M with speed ranging from 250Mhz to 1333Mhz. Delivering product on time and contribute greatly to company profits. - Technical lead on LL65nm 1M to 64M Platform Ultra Low Power Serial Interface SRAM.

Santa Clara, CA

Part of seven member start-up team. Custom design 18M CAM (Content-Addressable-Memory) core array and data path in 65nm. CAM device is configurable to provide parallel searches. Company was acquired for $7.7M by ISSI.

Santa Clara, CA

- Founding team member. Design all asynchronous and synchronous 1M/4M/9M/18M SRAM and 18M dual port SRAM using 0.35um, 0.25um, 0.18um TSMC technologies. SRAM devices were used as TSMC technology vehicles. Company was acquired for $200M by Cypress in 2000- Design very first CAM (content-addressable-memory) memory core array and data path for Netlogic.

Santa Clara, CA

4 person team leader to design a Reservation unit for Pentium processor.

San Jose, CA

- Design 66Mhz 256K synchronous SRAM used as L2 cache for x386 Intel microprocessor.- Design 66Mhz 256K synchronous FIFO, industry first fastest and highest density FIFO at the time.

San Jose, CA

Design team member on 64K and 256K Bi-CMOS Asynchronous SRAM.

Milpitas, CA

Design ECL standard cells, ECL and TTL I/O cells.