Thomas Chapin Email and Phone Number
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Motivated and a goal oriented technical professional with 25+ years of test engineering experience, covering all aspects of the product life cycle and several product types including microprocessors, System-on-Chip, embedded DRAM, flash, and chipsets.Adept at creating and implementing quality sort test programs, leading successful sort working groups, providing comprehensive first silicon checkouts, data collection, point-on data analysis, round-the-clock floor support, and detailed ISO 9000 change control documentation. This work all supports the ultimate test engineering goals of screening bad/marginal parts out in the quickest way possible while providing customers the right amount of data to improve the process.As an active member in a technical review board, I facilitated quality sort test program releases through reviewing ISO 9000 change control documentation and enforcing/standardizing validation work for changes being implemented.Skills:• Collaboration - by sharing in the test quality forums, conferences, across product groups, and improving business relationships (Design, Fab processes, Yield, Quality and Reliability, etc);• Communication - by presenting test solutions in written standards and orally to large groups (Microsoft Word & PowerPoint);• Lean Manufacturing - by active participation in a Lean team as a contributor, assisting in the creation of a sort working group chair handbook and continual optimization of the sort program release process;• Mentoring Peers - Expanded technical skills and competencies within working group;• Semiconductor Testing – by developing testing for various products for DC, Structural and Functional;• Multitasking – by balancing test development and product test program project management at a working group level;• Analysis – by collecting and evaluating data to determine process/product issues utilizing JMP or Excel tools.
Advantest
View- Website:
- advantest.com
- Employees:
- 1702
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Senior Application EngineerAdvantest Jul 2021 - PresentPortland, Oregon Metropolitan Area -
Senior Wafer Sort Test EngineerSamsung Austin Semiconductor Nov 2015 - Jul 2021Austin, Texas AreaComplete NPIs, release test programs, and perform unit level debug in support of quicker feedback to the factory. Integrate test programs from three external customers into our test environment including tester configuration, tester interface, and external collateral by working with vendors, floor technicians, and the customer. Coordinate tester configuration changes in order to align with new product needs. Includes setting up new workstations as well as updating existing ones to… Show more Complete NPIs, release test programs, and perform unit level debug in support of quicker feedback to the factory. Integrate test programs from three external customers into our test environment including tester configuration, tester interface, and external collateral by working with vendors, floor technicians, and the customer. Coordinate tester configuration changes in order to align with new product needs. Includes setting up new workstations as well as updating existing ones to meet minimum requirements. Maintain and update interface code to run wafers to work on our environment and desired features. Show less -
Senior Product Development EngineerIntel Corporation - Manufacturing Development Aug 2013 - Jul 2015Portland, Oregon Metropolitan AreaDelivered and validated test programs to support the development of “advanced test technology” to drive a >2x test cost reduction over the next 3 years. Recently certified the resulting technology to run in production with anticipated cost savings due to increased Assembly/Test yield and manufacturing capital savings. -
Senior Sort Product Development EngineerIntel Corporation - Product Health Enhancement May 2010 - Aug 2013Portland, Oregon Metropolitan AreaLed wafer sort testing development for embedded DRAM memories on the 22 nm process, the first of its kind at Intel. Implemented dual socketing at sort to aid in the unique screening requirements for DRAM cells. First hot temperature testing done at wafer level in production outside of flash memories at Intel. -
Senior Sort Product Development EngineerIntel Corporation - Aloha Factory Operations Jul 2006 - May 2010Portland, Oregon Metropolitan AreaPerformed wafer sort testing for both CPU and chipset devices (Core 2, Core 2 Duo, and one Core 2 mobile north bridge chipset) on the 65 nm process. Led the start-up and transfer of 65 nm chipset technology at sort across the virtual factory using the north bridge product. Helped to sustain the test floor by maintaining statistical process control limits for assigned products as well as being the first line of defense for debugging and providing direction on reacting to any testing… Show more Performed wafer sort testing for both CPU and chipset devices (Core 2, Core 2 Duo, and one Core 2 mobile north bridge chipset) on the 65 nm process. Led the start-up and transfer of 65 nm chipset technology at sort across the virtual factory using the north bridge product. Helped to sustain the test floor by maintaining statistical process control limits for assigned products as well as being the first line of defense for debugging and providing direction on reacting to any testing issues requiring assistance. Show less -
Sort EngineerIntel Corporation - Fab 17 Sort Jun 2001 - Jul 2006Hudson, Massachussetts AreaPerformed wafer sort testing for both CPU and chipset devices (Pentium 3, Pentium 4, and 2 south bridge chipsets) on the 130 nm process. Created and implemented sort test programs, led sort working groups, first silicon checkout, data collection, data analysis, floor support, and ISO 9000 change control documentation. As sort working group chair focused on program development/integration as well as providing direction and setting goals and roadmaps for the sort working group. Chipset… Show more Performed wafer sort testing for both CPU and chipset devices (Pentium 3, Pentium 4, and 2 south bridge chipsets) on the 130 nm process. Created and implemented sort test programs, led sort working groups, first silicon checkout, data collection, data analysis, floor support, and ISO 9000 change control documentation. As sort working group chair focused on program development/integration as well as providing direction and setting goals and roadmaps for the sort working group. Chipset product management requirements included two concurrent steppings with flex equivalents (4 different sort programs) which spanned three different sort sites. Sort product engineer involved in the start-up and qualification of the 130 nm (using Pentium 3 product) process at multiple sort sites. Show less -
Td Sort EngineerIntel Corporation - Sort/Test Technology Development Jul 2000 - May 2001Portland, Oregon Metropolitan AreaTrained for 10 months with wafer sort test development on the Pentium 3 CPU device using the 130 nm process. Integrated and implemented sort programs, first silicon checkout, data collection, data analysis, and ISO 9000 change control documentation. Assisted in developing and supervising the release of sort test programs to the fab (code edits, ISO 9000 change control documentation and presentation, checkout, and correlation). -
Product EngineerIntel Corporation - Flash Product Group Jun 1996 - Jun 2000Sacramento, California AreaWorked for 3+ years with wafer sort testing and <1 year with class testing on flash memories (NOR technology). Formed and executed sort test programs, first silicon checkout, data collection, data analysis, 94 spec, and authored ISO 9000 change control documentation. Coordinated the initial start-up of one of Intel’s products with a sub-contractor factory in Japan. Fostered the necessary sort program changes and handled ordering of hardware and probe cards for the… Show more Worked for 3+ years with wafer sort testing and <1 year with class testing on flash memories (NOR technology). Formed and executed sort test programs, first silicon checkout, data collection, data analysis, 94 spec, and authored ISO 9000 change control documentation. Coordinated the initial start-up of one of Intel’s products with a sub-contractor factory in Japan. Fostered the necessary sort program changes and handled ordering of hardware and probe cards for the start-up. Completed the first silicon sort checkout locally by sorting wafers, generating/presenting updates, and identifying possible issues seen during sort. Show less
Thomas Chapin Skills
Thomas Chapin Education Details
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Electrical And Electronics Engineering -
Engineering Science
Frequently Asked Questions about Thomas Chapin
What company does Thomas Chapin work for?
Thomas Chapin works for Advantest
What is Thomas Chapin's role at the current company?
Thomas Chapin's current role is Senior Application Engineer at Advantest.
What is Thomas Chapin's email address?
Thomas Chapin's email address is ta****@****ail.com
What schools did Thomas Chapin attend?
Thomas Chapin attended Rochester Institute Of Technology, Alfred State College - Suny College Of Technology.
What are some of Thomas Chapin's interests?
Thomas Chapin has interest in Volleyball, Children, Spending Time With Family, Environment, Education, Science And Technology, Running, Health, Movies, Video Games.
What skills is Thomas Chapin known for?
Thomas Chapin has skills like Product Development, Ate, Lean Thinking, Agile Methodologies, Scrum, Teamwork, Microsoft Office, Jmp, Tortoise Svn, Git, Microsoft Excel, Microsoft Word.
Who are Thomas Chapin's colleagues?
Thomas Chapin's colleagues are Jooyea Han, 佐治孝一, Johnson Tsai, Park Kiyoung, Nicole Turner, 岡崎総一郎, Htet Htet Aung.
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Thomas Chapin
Real Estate Investor In Single Family And Small Multi-Family Homes, Licensed Realtor At Mid South RealtyParon, Ar -
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