• Lead of SerDes analog design team in Datacom department. • Responsible for delivering SerDes IPs (PCIe Gen I/II, 1000Base-X, SGMII, QSGMII, XAUI, RXAUI and XFI) to different product lines, including Processor, Wi-Fi, Ethernet PHY/Switch, printer, disk array controller and SSD controller. One of the product was the industrial first PCIe SSD controller used in PC and it brought in 50 million revenue per quarter for the company. • Designed and carried out from initial design phase to production analog blocks in - 0.15um/0.13um, 90nm/80nm, 65nm/55nm, 40nm, 28nm and 16nm/12nm CMOS technologies. • Designed and carried out from conception to production analog blocks that include the following: - 625MHz to 6.25GHz PLLs - Clock & Data Recovery (CDR), DLL and Phase Interpolator circuits - Equalizer and De-serializer circuits - Driver and Serializer circuits- Eye Monitor circuits- Bandgap and IVREF blocks - Power-on Reset and Power Monitor circuits - Temperature sensor - LDO and switched-capacitor regulator - Top level analog integration • Coordinated with teams to define SerDes architecture and generate the design specifications for analog blocks. • Worked with the customer on the requirements of analog IPs and coordinated to put USB, PCIe, HDMI, FE, Clock driver, Fan driver, PLLs, JTM, etc. into the chipset of the video game console. • Implemented debugging techniques with analog designers, system engineers and application engineers to resolve any issue within analog domain. • Facilitated careful design considerations with system engineers to come up with evaluation board design, ATE test board and final board designs. • Trained young but energetic engineers to efficiently design, layout and test analog designs.

• Designed high-speed I/O interface blocks in 80nm and 65nm CMOS technologies for graphic cards and chipsets including the following - Clock buffer and clock distribution circuits - PFD, Charge-pump, and loop filter circuits in PLL

• Designed and delivered Analog blocks for different product lines including the following: - Ethernet/Fast Ethernet transmitters in 0.35um/0.22um CMOS technologies - Intel P4 and AMD K8 chipset PLLs in 0.22um/0.15um CMOS technologies - 802.11a/b/g WLAN baseband chipset high speed, high resolution DACs in 0.22um/0.18um CMOS technologies - Bandgap circuit in 0.18um CMOS process- Crystal Oscillator circuit in 0.18um CMOS process• Evaluated and characterized the designed circuits in silicon. • Established testing items and procedures for system engineers and helped customers to solve system issues.