Lead designer of TRAPv4, a fourth generation novel TRAnsistor-level Programmable fabric for secure and cost-effective IC redaction. I introduced SRAM based programming and a variety of architecture and physical design improvements, achieving massive PPA improvements over prior versions of TRAP. I led a team of several PhD students through the development of three prototype tape-outs in Global Foundries 12LP technology. To support this technology, I developed a CAD flow using primarily commercial ASIC design tools (Cadence) for automatic Verilog-to-GDS and Verilog-to-Bitstream flows.

Worked on circuit design techniques to prevent reverse engineering (RE) of integrated circuits (ICs). Theft/piracy of ICs by RE poses a major economic threat to the semiconductor industry. IC camouflaging can thwart RE attacks. In one embodiment of IC camouflaging, the layout of logic gates is designed to look identical. A camouflaged layout incurs significant area, power, and delay overhead, prohibiting their application in commercial designs. My research objective is to build a framework for automatic generation of camouflaged layouts with minimal overhead for a given set of Boolean function. The layouts can then be included in commercial designs to provide defense against reverse engineering attacks.

Research and design of a Thermoelectric Energy Harvesting system to provide power for embedded processing and sensing systems that can improve medical care and enhance lives.