Thomas Loftus Email & Phone Number

Manhattan Beach, CA, US

Manhattan Beach, CA, US

Manhattan Beach, CA, US

Falls Church, VA, US

Falls Church, VA, US

Planning for Integration and Test of ASIC to be fabricated and delivered in late 2023.

Falls Church, VA, US

Completed a 2 year High Speed I/O (HSIO) Prototype ASIC test activity to burn down significant product risk in the development phase of a processor to be fabricated in late 2023. Responsible for planning and completing the activity from start to finish. I worked with facilities to prepare lab, install cooling, electrical, and support for 6 engineering.

Falls Church, VA, US

Leading a talented multi-disciplinary team developing, verifying, integrating, and testing advanced technology SoC products for demanding defense applications.

Current Project:Using Xilinx Vivado 2014.4 and Eclipse SDK on Centos 6.6 linux system to develop an FPGA based embedded system using a Xilinx Zynq XC7Z020 with ARM dual Cortex A9 core and custom logic coded in VHDL and Verilog. Avnet Zedboard based prototype platform.

Germantown, MD, US

Managed R&D and administrative activities in the Availink (US) office for the CEO. Remodeled offices and renegotiated lease to improve work environment and reduce monthly costs by 20%. Improved product test and verification efficiency for CTO by adding new debug features to test software and firmware. Maintained high availability and security for Windows.

Germantown, MD, US

Directed Hardware and Physical Design teams creating consumer satellite and terrestrial receiver/demodulator IC's through complete ASIC design flow from specification to tapeout.Performed individual design, verification, analysis, and test tasks to supplement team resources using a variety of industry leading tools, languages, and scripting such as.

Falls Church, VA, US

Managed a team providing program management, technical support, requirements development, system design, and technical leadership on a range of space equipment development contracts and IRAD projects. Supported new business acquisitions and definition and evaluation of advanced technologies for use in ongoing and future programs.

Marlborough, MA, US

Lead front end designer for battery powered, mixed signal wireless transceiver ASIC in TSMC 0.18um process. Architecture design, hardware design, Verilog coding, RTL and gate verification, interface with physical design team.

Germantown, MD, US

Chip lead on two ASIC's, team member on two others. Front end development in Verilog using Cadence NC. Installed and configured synthesis and timing tools for ASIC team. LSF and scripting for regressions.

System Engineer for Large Capacity Solid State Recorder (SSR) project for NASA Goddard Space Flight Center (Hubble Space Telescope) responsible for interpreting specifications, partitioning system, and directing a team of design engineers in the implementation. I implemented a complex radiation tolerant, FPGA based, DRAM Controller design with EDAC.

Msee, Electrical Engineering

Bsee, Electrical Engineering