Design Engineer
~ Focused on building, testing, and shipping HDL to support Opal Kelly’s line of FPGA integration modules and other products~ Took an active role in every stage of product lifecycle from early roadmapping to finishing touches andlifecycle support~ Trained, oversaw, and managed an FPGA design intern working through multiple HDL projects~ Planned and oversaw software development releases~ Contributed significantly to the development of the SYZYGY standard for FPGA peripherals~ Developed IP for numerous different physical interfaces from simple single-ended serial to high speedLVDS including static timing analysis and simulation~ Authored extensive customer facing and internal documentation~ Tested and debugged analog and digital designs through the use of the Vivado ILA, oscilloscopes, spectrum analyzers, and thermal imaging tools~ Built a high data rate, reliable inter-FPGA communication system based on the Xilinx Aurora IP~ Leveraged the Yocto project to develop a custom Linux distribution for a Zynq SoC FPGA product~ Developed an image capture application for the Zynq SoC utilizing Xilinx DMA IP to pass data betweenthe programmable logic and CPU memory~ Designed and built a circular frame buffer memory controller for image sensor evaluation leveraging DDR3 and DDR4 memory and supporting numerous physical interfaces and FPGA products~ Involved in schematic and layout design reviews for advanced FPGA PCB designs including DDR3, DDR4, and multi-gigabit transceiver interfaces~ Participated in and contributed to software code reviews~ Managed continuous integration infrastructure for software development including provisioning andsupporting multiple Linux distributions
