Thomas Varga Email & Phone Number

Baltimore, Md, Us

Linthicum, Maryland, United States

Responsible for developing complex tool flows and IP for superconducting RQL (reciprocal quantum logic) requiring the invention of new methodologies, tools and flows. Generated IP requiring many thousands of interdependent views as required by commercial and many home-grown tools. Developed an efficient, high quality build system to automate all aspects of design, analysis, characterization, verification and regressions.• Develop highly optimized synthesis/placement flow based on genus and innovus.• Debug and support custom routing solution.• Generate test libraries for new superconducting technology node.• Coordinate with management, project teams and partners using Agile based program management.• Promoted and directed the implementation of high quality testbench library used for design, margin analysis and characterization• Authored many tools to enable automated parallelized simulation, analysis and generation of extracted data• Developed flows to generate and test libraries containing WPL (wave pipeline logic) and PML (phase mode logic) stdcells, IO and macros• Promoted and directed development of next generation libraries and methodologies to support future process nodes• Promoted and led continuous improvement of flows and tools across many groups• Nominated for 2020 Northrop Grumman Presidential Award for Quality Excellence

Linthicum, Maryland, United States

• Developed a sophisticated flow automation system in Python to enable highly efficient, parallelized builds including automated md5 cksum based dependency tracking of thousands of views and files.• Designed to guarantee reproducible high throughput, correct-by-construction builds, QA and release processes.• Wrote hundreds of scripts for generating and qualifying data and views.• Integrated downstream tools to automatically confirm IP correctness for performance, margin, interfaces and routability.• Helped with qualifying optimized cloud based IT infrastructure and IP build system.

Columbia, Maryland, United States

Responsible for developing an efficient, high quality flow automation system to automate all aspects of physical design, verification, analysis and characterization of IP. Responsible for defining methodology, integrating and qualifying CAD tools and results for DRC, LVS, DFM, DFY, extraction and characterization. Interfaced and coordinated with foundry, tool developers and customers to qualify and optimize delivered IP.• Specified and developed highly optimized IT infrastructure and IP generation system. - Written in Python to enable highly parallelized generation and tracking of thousands of views and files. - Scripted automated qualification of views through tools such as Crossfire, Genus, Tempus, and Innovus.• Developed a Python based gds layout generating and manipulating tool. - Includes Boolean engine to enable using bloats, shrinks, xor etc to manipulate layouts. - Used to automatically generate extraction frames as well as Vt and gate-length variant layouts.• The build system is used by many engineers to automate all aspects of design, analysis, quality assurance, final build and delivery of IP.• Developed an automated characterization and verification flow based on Liberate, Variety and Liberate LV - Supports multiple vendor libraries, processes and all cell types including all power management cells - Generates AOCV, LVF, noise and EM liberty data in ECSM and CCS formats - Full verification of data including Monte Carlo vs LVF for process skewed and mean-shifted OCV• Defined and developed all QA and extraction methodologies and qualified all results. - Maximized throughput to minimize production risks and enable quick updates. - Verified 7K cell library in 2 hours - Characterization with LVF in 48 hours. - Integrated downstream tools to confirm IP correctness for performance, density, architecture, interfaces and routability.• Successfully met all goals by delivering large custom libraries for multiple technology nodes.

Waltham, Ma

Responsible for generating and delivering world-class IP optimized for PPA. Optimized circuits, layout, architecture and performance with a large number of EDA tools on leading edge technologies. Continuously drove innovation to enhance tools, flows and methodologies used world-wide by dozens of engineers to deliver world-class, next generation (16nm FinFET) zero-defect libraries..• Developed automated automation system for designing, analyzing, verifying, characterizing and releasing stdcell and IO libraries. Enabled optimized, high throughput, correct-by-construction, repeatable development process. - Used to deliver world-class, next generation (16nm FinFET) zero-defect libraries optimized for area, performance and power. - Highly parallelized, high throughput system used to build and deliver huge libraries that are 100% quality assured and on schedule. - Integrated many downstream tools to automatically confirm library correctness for performance, density, architecture, interfaces and routability. - Developed Cadence Virtuoso based hierarchical layout methodology. - Characterized libraries using NCX/HSPICE to generate liberty/db files and verify performance. - Developed and evaluated libraries in conjunction with IC Compiler chip-level flow development.• Continuously integrated new tools into flow such as Cadence Virtuoso, Milkyway and IC Compiler to automatically build and qa all required library views. - Wrote hundreds of tools for point solutions, analysis and qa

Waltham, Ma

Managed a group chartered to develop tools and flows to automate the generation of stdcell and IO libraries. • Managed development of Library Development system, a change management and automation system.• Enhanced the design environment and circuit development infrastructure.• Drove evaluation and adoption of tools and methodologies to improve library quality and time to market.

Waltham, Ma

• Responsible for circuit design, layout and characterization of stdcells and IO.• Responsible for characterization of all libraries.• Developed automated build, qa and delivery system.• Developed ICGen-based layout automation infrastructure and integrated it into library automation system.

Waltham, Ma

• Lead Layout effort on 250K+ transistor I/O control chip. Provided support to logic design effort and performed floorplanning, power system analysis and routing of the chip.• Heavily involved in defining and implementing the methodology for chip development.• Proposed and wrote many software tools to implement a CAD environment allowing completely automatic generation, characterization, verification and documentation of all cell compilers.• Circuit design and development of configurable 16K Dynamic and Static RAM generators.• Designed a configurable PLA generator with automatic device sizing for optimum high speed performance. It also had many timing and control options enabling customization for each application. • Designed many of the generators for a CMOS library with automated characterization and documentation.• Designed complex Cache tag and store generators. Implemented as a high density macro including SRAM, parity, compare, mux and busdriver functions.

M.S.E.E, Electrical Engineering

Concentration in VLSI design and advanced computer architectures

B.S.E.E., Electrical Engineering