Thomas Varga Email & Phone Number

Baltimore, MD, US

Linthicum, Maryland, United States

• Responsible for developing complex tool flows and IP for superconducting RQL (reciprocal quantum logic) requiring the invention of new methodologies, tools and flows. Generated IP requiring many thousands of.
• Develop highly optimized synthesis/placement flow based on genus and innovus.
• Debug and support custom routing solution.
• Generate test libraries for new superconducting technology node.
• Coordinate with management, project teams and partners using Agile based program management.
• Promoted and directed the implementation of high quality testbench library used for design, margin analysis and characterization

Linthicum, Maryland, United States

• Developed a sophisticated flow automation system in Python to enable highly efficient, parallelized builds including automated md5 cksum based dependency tracking of thousands of views and files.
• Designed to guarantee reproducible high throughput, correct-by-construction builds, QA and release processes.
• Wrote hundreds of scripts for generating and qualifying data and views.
• Integrated downstream tools to automatically confirm IP correctness for performance, margin, interfaces and routability.
• Helped with qualifying optimized cloud based IT infrastructure and IP build system.

Columbia, Maryland, United States

• Responsible for developing an efficient, high quality flow automation system to automate all aspects of physical design, verification, analysis and characterization of IP. Responsible for defining methodology.
• Specified and developed highly optimized IT infrastructure and IP generation system. - Written in Python to enable highly parallelized generation and tracking of thousands of views and files. - Scripted automated.
• Developed a Python based gds layout generating and manipulating tool. - Includes Boolean engine to enable using bloats, shrinks, xor etc to manipulate layouts. - Used to automatically generate extraction frames as well.
• The build system is used by many engineers to automate all aspects of design, analysis, quality assurance, final build and delivery of IP.
• Developed an automated characterization and verification flow based on Liberate, Variety and Liberate LV - Supports multiple vendor libraries, processes and all cell types including all power management cells.
• Defined and developed all QA and extraction methodologies and qualified all results. - Maximized throughput to minimize production risks and enable quick updates. - Verified 7K cell library in 2 hours.

Waltham, MA

• Responsible for generating and delivering world-class IP optimized for PPA. Optimized circuits, layout, architecture and performance with a large number of EDA tools on leading edge technologies. Continuously drove.
• Developed automated automation system for designing, analyzing, verifying, characterizing and releasing stdcell and IO libraries. Enabled optimized, high throughput, correct-by-construction, repeatable development.
• Continuously integrated new tools into flow such as Cadence Virtuoso, Milkyway and IC Compiler to automatically build and qa all required library views. - Wrote hundreds of tools for point solutions, analysis and qa

Waltham, MA

• Managed a group chartered to develop tools and flows to automate the generation of stdcell and IO libraries.
• Managed development of Library Development system, a change management and automation system.
• Enhanced the design environment and circuit development infrastructure.
• Drove evaluation and adoption of tools and methodologies to improve library quality and time to market.

Waltham, MA

• Responsible for circuit design, layout and characterization of stdcells and IO.
• Responsible for characterization of all libraries.
• Developed automated build, qa and delivery system.
• Developed ICGen-based layout automation infrastructure and integrated it into library automation system.

Waltham, MA

• Lead Layout effort on 250K+ transistor I/O control chip. Provided support to logic design effort and performed floorplanning, power system analysis and routing of the chip.
• Heavily involved in defining and implementing the methodology for chip development.
• Proposed and wrote many software tools to implement a CAD environment allowing completely automatic generation, characterization, verification and documentation of all cell compilers.
• Circuit design and development of configurable 16K Dynamic and Static RAM generators.
• Designed a configurable PLA generator with automatic device sizing for optimum high speed performance. It also had many timing and control options enabling customization for each application.
• Designed many of the generators for a CMOS library with automated characterization and documentation.

M.S.E.E, Electrical Engineering

Concentration in VLSI design and advanced computer architectures

B.S.E.E., Electrical Engineering