Thomas Young Email & Phone Number

San Jose, Ca, Us

. Lead design team to integrate and verify Adaptrum base band processor into AXI fabric based SOC. Design GPS synchronization among base stations for wireless communication in TV white space. Design memory token, share memory, mail box for multiple base band processors for sharing resources. Design of RTL to enhance for multiple-user from single-user, QAM256 from QAM64, AXI from GPMC. Work with architecture team to define MATLAB data format for Adaptrum base band IP verifications. Achieve pin mapping, synthesis, P&R for Kintex & Cyclone working images in FPGA base/client systems. Implement in house trace analyzer, capture memory, and ILA triggering logic for FPGA debug in the lab. Collaborate with design house to integrate IPs such as ARC700, DDR3, USB, GMAC, DMA, SD in AXI fabric . Support with contractors to build UVM in full SOC verification on top of existing Verilog test environment . Work with firmware engineer for driver support in newly developed hardware features and bug fixes. Provide Synopsys DC and Formality scripts to our design house for Adaptrum BB for ASIC tape out. Use Spyglass & gate level SDF annotation simulation to check multiple clock domain crossing. Successfully finish the tape out process to have design house release GDS to manufacturing foundry

Menlo Park, Ca, Us

. Designed and module verified the physical layer of the USB-C power delivery specification. Implemented the AHB wrapper logic for Flash and NVM IP in next generation mix-signal IC. Integrated ARM Cortex M0 core and building AHB bridges to communicate internal Finsix logic . Worked with analog engineers to come up unique power up sequence controlled by digital SM . Simulated the digital RTL by using Verilog and built test cases for coverages.. Wrote Python scripts to interface FTDI USB-Serial conversion for in house prototype tester. Synthesized RTL into Artix-7 FPGA to test the digital portion in mixed signal IC. Successfully tapeouted, tested and made in the production of the first Finsix mixed signal IC . Used Cadence tools as followings for digital portion of mix-signal IC:. Ran RTL and Gate Level simulation. Complied RTL with DFT insertion. Generated ATPG test patterns for scan coverage . Created floorplan for digital block layout

. Designed next generation of Cloud Computing chip with improved visual quality and bandwidth . Implemented and verifying a new 2D engine with new up and down scaling capabilities . Upgraded from previous DDR2 IP to newer DDR3; PCIE1.0 IP to newer PCIE2. Integrating H.264 video decoder IP with AXI interface for Microsoft Window 8 requirement. Wrote test programs in C to verify both register and memory access for system in house diagnostic . Successfully worked with UMC to produce first working silicon for Cloudvue RemoteFX accelerator ASIC

Redmond, Washington, Us

Defined and designed various blocks inside the RemoteFX server and client hardware including . Discrete Waveform Transform, Quantization, Run-Length, . RGB/YUV display & cursor unit, color space conversion, . DMA, buffer management unit, MIU wrapper with arbitration logic for DDR2 IP. An external host bus interface unit which communicated with the ARM-9 based Atmel SOC. Used Synlicity to synthesis various working FPGAs images in Xilinx Spartan and Virtex families . Collaborated with eASIC to tapeout a working Gate-Array chip for Microsoft Demo in WINHEC Tapie

Us

. Prototyped various hardware modules using Virtex5 and Spartan3 FPGA . Designed wavelet codec engine, cross-bar fabric, memory and display controller in Verilog

. Designed internal blocks and integrated external IPs in a SOC for the cell phone media accelerator. . Based on AMBA 2.0 bus architecture with a SRAM controller, display unit, audio unit, DMA, 2D. Integrated IPs including SDCARD interface, NDFLASH interface, TV Encoder, USB 2.0 OTG controller

Us

. Defined, implemented, verified, and debugged the VLD in both the CAVLC and CABAC . Partitioned and created a boundary between firmware code and above VLD . Coded VLD test bench with PLI interface to initialize VLD parameters for testing

. Synthesized design from RTL to gate; Performed functional validation between RTL and gat. Stitched scan chains together for scan; Used static timing tool to analyze the full chip

Defined and designed the Egress Storage and the Local Buffer Manager ASIC for OC-192 LCWrote testbench and verified features in Traffic Manager ASIC for OC-48 LC

Us

Defined, designed, and verified 3D, 2D, MPEG, Display in the S3’s Savage family products Designed test version of graphic card to test S3 1st generation graphic accelerator

Santa Clara, California, Us

Defined, designed validation test vehicles for various 486 and Pentium processors.Wrote test vectors on Trillium tester for mix signals modem chip

Ca

Created simulation model for Apple Link which interfaced between Macintosh and Micro-Vax.

Master Of Science (M.S.), Electrical And Electronics Engineering

Bachelor Of Science, Electrical And Electronics Engineering