Thomas Young's Location
San Mateo, California, United States, United States
Thomas Young's Contact Details
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About Thomas Young
Experienced Senior Staff Engineer with a demonstrated history of working in the information technology and services industry. Skilled in SystemVerilog, Firmware, Hardware Architecture, Imaging Processing, Digital Signal Processors, and System on a Chip (SoC). Strong information technology professional with a Master of Science (M.S.) focused in Electrical and Electronics Engineering from San Jose State University.
Thomas Young Work Experience Details
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Sr. Staff Engineer And Team LeadAdaptrum Apr 2017 - PresentSan Jose, Ca, Us. Lead design team to integrate and verify Adaptrum base band processor into AXI fabric based SOC. Design GPS synchronization among base stations for wireless communication in TV white space. Design memory token, share memory, mail box for multiple base band processors for sharing resources. Design of RTL to enhance for multiple-user from single-user, QAM256 from QAM64, AXI from GPMC. Work with architecture team to define MATLAB data format for Adaptrum base band IP verifications. Achieve pin mapping, synthesis, P&R for Kintex & Cyclone working images in FPGA base/client systems. Implement in house trace analyzer, capture memory, and ILA triggering logic for FPGA debug in the lab. Collaborate with design house to integrate IPs such as ARC700, DDR3, USB, GMAC, DMA, SD in AXI fabric . Support with contractors to build UVM in full SOC verification on top of existing Verilog test environment . Work with firmware engineer for driver support in newly developed hardware features and bug fixes. Provide Synopsys DC and Formality scripts to our design house for Adaptrum BB for ASIC tape out. Use Spyglass & gate level SDF annotation simulation to check multiple clock domain crossing. Successfully finish the tape out process to have design house release GDS to manufacturing foundry -
Sr. Digital EngineerFinsix Corporation Mar 2014 - Apr 2017Menlo Park, Ca, Us. Designed and module verified the physical layer of the USB-C power delivery specification. Implemented the AHB wrapper logic for Flash and NVM IP in next generation mix-signal IC. Integrated ARM Cortex M0 core and building AHB bridges to communicate internal Finsix logic . Worked with analog engineers to come up unique power up sequence controlled by digital SM . Simulated the digital RTL by using Verilog and built test cases for coverages.. Wrote Python scripts to interface FTDI USB-Serial conversion for in house prototype tester. Synthesized RTL into Artix-7 FPGA to test the digital portion in mixed signal IC. Successfully tapeouted, tested and made in the production of the first Finsix mixed signal IC . Used Cadence tools as followings for digital portion of mix-signal IC:. Ran RTL and Gate Level simulation. Complied RTL with DFT insertion. Generated ATPG test patterns for scan coverage . Created floorplan for digital block layout -
Co-FounderCloudvue Technologies Oct 2010 - Mar 2014. Designed next generation of Cloud Computing chip with improved visual quality and bandwidth . Implemented and verifying a new 2D engine with new up and down scaling capabilities . Upgraded from previous DDR2 IP to newer DDR3; PCIE1.0 IP to newer PCIE2. Integrating H.264 video decoder IP with AXI interface for Microsoft Window 8 requirement. Wrote test programs in C to verify both register and memory access for system in house diagnostic . Successfully worked with UMC to produce first working silicon for Cloudvue RemoteFX accelerator ASIC
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Sr. Hardware DeveloperMicrosoft Jan 2008 - Sep 2010Redmond, Washington, UsDefined and designed various blocks inside the RemoteFX server and client hardware including . Discrete Waveform Transform, Quantization, Run-Length, . RGB/YUV display & cursor unit, color space conversion, . DMA, buffer management unit, MIU wrapper with arbitration logic for DDR2 IP. An external host bus interface unit which communicated with the ARM-9 based Atmel SOC. Used Synlicity to synthesis various working FPGAs images in Xilinx Spartan and Virtex families . Collaborated with eASIC to tapeout a working Gate-Array chip for Microsoft Demo in WINHEC Tapie -
Senior Member Of Technical StaffCalista May 2006 - Dec 2007Us. Prototyped various hardware modules using Virtex5 and Spartan3 FPGA . Designed wavelet codec engine, cross-bar fabric, memory and display controller in Verilog -
Senior Staff Design EngineerFangtek Inc Apr 2005 - Apr 2006. Designed internal blocks and integrated external IPs in a SOC for the cell phone media accelerator. . Based on AMBA 2.0 bus architecture with a SRAM controller, display unit, audio unit, DMA, 2D. Integrated IPs including SDCARD interface, NDFLASH interface, TV Encoder, USB 2.0 OTG controller -
Sr. Design EngineerVweb Corporation Nov 2003 - Apr 2005Us. Defined, implemented, verified, and debugged the VLD in both the CAVLC and CABAC . Partitioned and created a boundary between firmware code and above VLD . Coded VLD test bench with PLI interface to initialize VLD parameters for testing -
Design ManagerNational Semiconductor Jun 2002 - Nov 2003. Synthesized design from RTL to gate; Performed functional validation between RTL and gat. Stitched scan chains together for scan; Used static timing tool to analyze the full chip -
Member Of Technical StaffPluris Terabit Jun 1999 - May 2002Defined and designed the Egress Storage and the Local Buffer Manager ASIC for OC-192 LCWrote testbench and verified features in Traffic Manager ASIC for OC-48 LC
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Member Of Technical StaffS3 Graphics Apr 1993 - Jun 1999UsDefined, designed, and verified 3D, 2D, MPEG, Display in the S3’s Savage family products Designed test version of graphic card to test S3 1st generation graphic accelerator -
System Validation EngineerIntel Corporation Feb 1990 - Jun 1993Santa Clara, California, UsDefined, designed validation test vehicles for various 486 and Pentium processors.Wrote test vectors on Trillium tester for mix signals modem chip -
Co-Op EngineerNortel Networks Jan 1988 - Jun 1988CaCreated simulation model for Apple Link which interfaced between Macintosh and Micro-Vax.
Thomas Young Skills
Verilog
Asic
Soc
Fpga
Debugging
Embedded Systems
Rtl Design
Xilinx
Embedded Software
Ic
Pcie
Timing Closure
Hardware Architecture
Arm
System On A Chip
Usb
C++
3d Graphics
2d Graphics
Programming
Microprocessors
Eda
Application Specific Integrated Circuits
Simulations
Hardware
Linux
C
Computer Architecture
Firmware
Systemverilog
Integrated Circuits
Logic Synthesis
Primetime
Java
Digital Signal Processors
Processors
Field Programmable Gate Arrays
Pcb Design
Thomas Young Education Details
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San José State UniversityElectrical And Electronics Engineering -
California Polytechnic State University-San Luis ObispoElectrical And Electronics Engineering
Frequently Asked Questions about Thomas Young
What company does Thomas Young work for?
Thomas Young works for Adaptrum
What is Thomas Young's role at the current company?
Thomas Young's current role is Sr. Staff Engineer and Team Lead at Adaptrum.
What is Thomas Young's email address?
Thomas Young's email address is ty****@****six.com
What schools did Thomas Young attend?
Thomas Young attended San José State University, California Polytechnic State University-San Luis Obispo.
What skills is Thomas Young known for?
Thomas Young has skills like Verilog, Asic, Soc, Fpga, Debugging, Embedded Systems, Rtl Design, Xilinx, Embedded Software, Ic, Pcie, Timing Closure.
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