Thomas Ching Email & Phone Number

Fremont, Ca, Us

Fremont, Ca, Us

Santa Clara, California, Us

• Built HAPS prototyping ARM cores subsystem with NOC interface of PCIe, LPDDR5, MIPI Flash and USB.• Achieved much more efficient data and command/address tracing of CPU memory bus instruction sets by modifying and tuning Xilinx and Altera FPGA for the DEG/S3E/Trace Platform Technologies Group.• Facilitated efficient state machine RTL design to handle filter and data compression logic in VHDL.• Identified DDR4 2133 SDRAM and inter-connect FPGA timing issues and resolved with fixes.• Stratix 10 transceiver adaptive parametric tuning for DDR5 SODIMM interposer and host PCIe interface.• Built test benches and functional bus models for FPGA simulation.• Expertise in synthesis report analysis, timing analysis, and writing FPGA design constraints.• Successfully debugged logic and timing issues in the lab using Chipscope, SignalTap and Oscilloscope.• Designed and built DDR4 memory interposer PCB board.• Worked collaboratively with Intel group customers to deliver 2LM memory traces for architectural studies.

Santa Clara, Ca, Us

• Successfully prototyped and brought up on Dini SOC FPGA the 4G LTE Ultra Modem with RF and GPS.• Facilitated Xilinx Vivado synthesis, constraints, implementation, and ILA waveform debug.• Achieved low power target with clock gating power management and debugged timing issues.• Utilized DA-net Codescape Debugger to verify firmware for MIPS processor based MCU, ECU and MCP.• Identified logic and timing issues in the lab environment using Vivado ILA waveform and Oscilloscope with python script to verify JTAG, GPIO, I2C, SPI, UART, SIM, MIPI and Flash Memory interfaces.• Debugged logic from System Verilog UVM design verification test bench against Vivado ILA waveform.

Sunnyvale, California, Us

• Expert on bring-up and validation of SoC designs on HAPS80 and HAPS100 FPGA prototyping systems using Synopsys' ProtoCompiler and Synplify Premier synthesis, design partitioning and debugging tools.• Expert knowledge in FPGA methodologies including high speed design, serial protocols implementation and FPGA timing closure.• Extensive experience implementing designs on Virtex-7 and Ultra Scale FPGA devices using Xilinx Vivado.• Proficiency in Verilog, VHDL, System Verilog programming and Tcl scripting.• Hands-on working knowledge of virtual prototyping, transactors, and transaction-based verification.• Reviewed customer clock gating and clock synchronization scheme to provide valuable solutions.• Supported customer design reviews to improve FPGA partition efficiency.• Facilitated customer design implementation by holding IP ownership of High Speed TDM SerDes and clock synchronization module as the go to person for these specialized IP.• Identified potential logic and software flow bugs quickly by creating hardware test logic and software tcl scripts for regression testing of product releases.• Won major account by performing customer design evaluation, logic debug, and bring up in lab.• Met customer design goal by applying expertise in Certify RTL partition, Synplify Premier FPGA physical synthesis, system simulation, static timing analysis, and critical Xilinx Vivado timing and placement constraint. • Worked collaboratively with customers to deliver FPGA-based prototyping solutions, resolve technical issues, conduct product training and presenting articles on Solvnet.

•Accomplished design of RFID Class-1 Gen-2 and Class-3 ASIC tag with I2C interface and 64Kbit EEPROM memory by utilizing extremely low power management for long battery life.•Improved debug processes by utilizing state machine compiler, creating complex state diagram. •Improved design efficiency in area and power by defining architecture and specification, presenting findings, and reviewing with team.•Utilized Modelsim for Verilog design, functional verification and post-route simulation.•Synthesized with Synopsys Ultra DC Compiler, clock tree synthesis and Astro place and route.•Performed static timing analysis, critical path review and timing closure.•Attained maximum coverage by utilizing Maverick II test plan and test pattern generation. •Achieved first time working silicon by performing logic debug on Xilinx FPGA prototype board with solid logic confident sign off before tape out. •Enhanced logic verification by debugging logic in bring up board and utilizing Focus Ion Beam in metal fix.

•Succeeded in 533 Mbps with 266 Mhz clock by performing high speed DDR2 SDRAM Memory Interface IP logic design.•Attained RTL coding, synthesis, timing and functional verification, and post-layout timing closure by reviewing critical timing path and modifying logic to meet timing.

Us

•Enhanced receiver buffer unit of 5M gate, 4-port Hyper Transport switch ASIC design by implementing logic, ensuring no over-run or under-run of buffer.•Realized receiving 800Mhz double data rate at PHY interface and 250Mhz core clock using 0.13um technology by implementing buffer control signals between interfaces.•With thorough knowledge of network layer level 2-4, performed logic design on buffer management, command routing, address decode, data buffering/framing, UnitIDClump, CRC/Protocol error checking, and link width/frequency initialization.•Improved system performance by defining micro-architecture specification.•Met 100% coverage by implementing logic in Verilog, verifying functions with Verilog test bench by writing specialized test for different sets of command and data flow.•Performed Built-Gate logic synthesis with timing constraint, static timing analysis, critical path review, and timing closure.

* Responsible for the design of the controller unit between internal RSF interface to external DDR SDRAM and PCI interface in an 8 million gates intelligent network processor using 0.18 um technology* Research different control plane interface verses PCI interface* Define micro-architecture of logic block* Implementation of logic block in Verilog* Design verification with Vera and Verilog* Synthesize logic into gate level with design constraint* Static timing analysis and timing closure

* Responsible for the management of various signal processing design modules in Rosun’s ADSL chip* Verilog logic implementation, simulation and synthesis into gate level netlist and static timing analysis* Modules under management included Framer, Scrambler, Reed Solomon Encode/Decode, Interleaver, Bit-pack, Constellation, Gain Scaling, FEQ, FFT/IFFT, and Tone Detection

* Key contributor from architecture to production of several MPEG chips used in Video CD and DVD player* Video Bus Interface Unit from internal DRAM Controller to internal TV Encoder Line and pixel filter design for flicker-free interpolated images Pan & Scan and Letterbox filtering Raster Scan timing generation* Sub-picture, Graphic Overlay, Cursor, and On Screen Display blending with video for DVD-MPEG2* Audio output DAC interface unit supporting 6 channel AC3* Motion Compensation and Pixel Filtering* Responsibilities included Design Specification, Verilog code and simulation, Synopsys synthesis script, Floor Planning, Place and Route, SDF back-annotated simulation, Test vector generation, Debugging in prototype board, Micro-code Interface, Focus Ion Beam metal fix, and E-beam probe analysis

* Design specification to manufacturing of video compression hardware in a complete Video Conference System* Responsible for the design of DMAC, a direct Memory Access Controller that process data between Video Input Processor, Video Output Processor, Vision Processor, DSP, and the Reference Memory* Actel design of a first generation DMAC in the AT&T Video Phone application* Modular design, simulation, and test vector generation of Video Input Processor and Video Output Processor ASIC* Worked with software engineers in debugging board level, Vision Processor, and DSP using ADSP-2100 emulator* Test vector generation and production release to manufacturing of PAL and GAL on the video hardware board

* Engineering team member in the research and development of a FDDI Fiber Optic Universal Premises Network which integrate Token Ring, Ethernet, IBM 3270/5250, RS-232, V.35, System 3X, T1, and ISDN into a 100 Mbit/sec platform* Wrote specification and designed Main Modem Board which consisted of ECL logic at the Transmit/Receive interface. Generating polling signals for Time Division Multiplexing for each of the Access Modules* Designed and debugged four Actel field programmable gate arrays used on the Main Modem Board:MAC1: IEEE and node source/destination address detection, network message link protocol state machineMAC2: 8 Khz frame generation with external sync, Read/Write address control for Time Slot Switch Table, Access module polling module, Parity generation and detection, Network Message insert/extractPHY: 4-bit/5-bit and NRZI encode/decode, Elasticity Buffer for frame length adjustment. Frame symbols detection and frame loss indication, Error detection and correctionVBUF: Variable buffer read/write address generation, 1/2/4/125 us variable buffer delay modes