• Helped establish the III-V Center of Excellence at Albany's Center for Semiconductor Research (CSR)• Coordinated various Albany tenants in establishing III-V processing infrastructure • Leveraged SEMATECH and CSR resources for III-V business opportunities• Developed and managed III-V process integration projects• Worked with Environmental, Health, and Safety department to address EHS risks of III-V processing• Developed project plans for SEMATECH Core and Associate Member projects• Coordinated SEMATECH, SUNY-CNSE, and member resources to meet project objectives• Managed project plans to deliver value to members, partners, and SEMATECH• Worked with advisory groups and across internal divisions to develop Core Member project proposals• Worked with business development teams to identify and develop Associate Member project prospects• Developed integrated process flows for structures and devices for strategic business opportunities• Developed advanced measurement techniques for advanced semiconductor manufacturing

• 3D Integration - Developed an integrated Far BEOL Through-Silicon Via process - Developed in-line voltage contrast techniques for at-level TSV leakage detection - Electrically and physically isolated and fixed leaky TSVs by determine root cause leakage mechanism - Electrically characterized the effect of TSV processing on FEOL device performance - Integrated TSVs and deep-trench decoupling capacitors for IBMs first 3D product (Semtech) - Helped resolve TSV-related film stress and delamination issues• BEOL Integration - Developed advanced BEOL interconnect processes for 32nm technology that met process assumptions - Troubleshot electrical and reliability fails to determine root cause mechanisms and sucessfully implemented solutions - Stabilized material thermal instabilities by modifying material compositions and process conditions - Worked with unit process engineers to develop, optimize, and troubleshoot processes in BEOL flow• FEOL Integration - Designed and developed integrated FEOL processes for advanced CMOS technologies - Coordinated teams of unit process engineers and vendors in developing new process technologies - Coordinated device and materials characterization activities to support technology development - Utilized project management techniques in the execution of process integration activities - Introduced high-k dielectrics and metal electrodes into embedded DRAM trench capacitors at 32nm - Optimized device structure (gate and spacer etch) in 45nm and 90nm CMOS technologies - Developed trench capacitor and shallow trench isolation processes for 2 DRAM technology nodes - Evaluated invention disclosures for technical merit as invention development team member for 14 years

• Taught undergraduate physics courses

• Developed dielectric CVD processes for deep sub-micron CMOS manufacturing• Performed extensive materials characterization on advanced dielectric technologies

• Managed a two-year experimental program in microwave/plasma processing• Supervised technicians and student researchers• Held U.S. Department of Energy “Q” security clearance

• Conducted independent research in particle-plasma interactions• Developed high intensity acoustics technique for particle levitation• Applied microwave engineering, plasma production, vacuum, and electronics techniques• Consulted with researchers as resident expert in microwave plasma and acoustics techniques