► IC design• Design of low-power (uA range) switched-capacitor DC-DC converter• Top level system design using Verilog/Verilog-AMS• Top level verification of analog on top mixed mode power management chip in a noise sensitive environment• Automated verification flow using tcl and python• Layout of various analog blocks► Lab verification• Development of a lab framework based on python• Instrument driver development with regression test• Set up a fully automated and reconfigurable test-bench• Automated post measurement data processing and report generation• Participating on instrument selection and testing► Qualification• ESD and latch-up qualification• Debugging using IV curve and failure analysis (LIT, OBIRCH, …)• Proposed and implemented the ESD fixes► Wafer test• Participated to the wafer-test development on a mixed-mode chip• Debugging and yield improvement• Participated to the production ramp-up• Developed a python framework to analyze STDF data using python and bokeh► Manufacturing test• Participated to the manufacturing test implementation of a multi-chip platform.• Involved in the debugging and the yield improvement► IT/CAD• Contributed to the maintenance of the EDA tools• Collaboration with the EDA vendors to improve the flow• Contributed to improve the IT infrastructure and the workflow► University collaboration• Supervisor of a master student and a PhD student• Supervisor of a student help.

► Destinations • Eastern Europe, Russia, Mongolia, China and Vietnam crossing by train and bus (4 months) • Great tour of Australia (9 months) • New Zeland (2 months)► Activities/Jobs • Volunteering at Anak Ranch, Orkhon, Mongolia (3 weeks) • Kitchen hand at Via Napoli Pizzeria, Sydney, Australia (4 months) • Delivery man (bicycle) at Deliveroo, Sydney, Australia (3 months)

Part of the embedded power management design group to develop fine grain power management solution on the 28nm FDSOI digital SoC platform.► Design of an innovative switched capacitor converter in 28nm FDSOI: • Single input voltage architecture (1.8V) using multi-ratio topology and MIM capacitor distributed across the digital load to enhance the digital flow compatibility • Investigation and proposition of various control method (linear and non-linear) according to an analogue design flow • Experimental validation with 2 manufactured and characterised test-chips: compliant to the specifications►Design of a voltage regulator for SoC core body biasing based on a negative switched capacitor converter • Design of the architecture • Advisor of a subcontractor► Co-advisor of a master internship: analysis of multi-regulator power supply architecture • Proposal modelling of the power supply architecture • Interaction, cross talk and stability analysis • Case study of an existing architecture (SMPS+LDO) dedicated to RF SoC

• Design of switched capacitor DC-DC converters in 32nm bulk CMOS technology. • Efficiency and power density optimization for SoC application.