Thuvan Le Email & Phone Number

San Jose, CA, US

Suwon-Si, Gyeonggi-Do, KR

Senior Staff IC Layout Engineer specialize in custom SRAM design achieving requirement for PPA.- Lead the layout team successfully taped out FinFet 5nm, 4nm Samsung Technology -Innovated Layout Tool Automation

Austin, Texas, US

Microprocessor Senior IC Layout Designer specialize in custom Memory SRAM design from library leaf cell to top level blocks- Lead on FinFet 7nm project, TSMC process.-Cadence virtuoso - VXL - Super User, Place & Route using Virtuoso Base Space Router/track pattern-Innovated Layout Automation Tool.-Worked experience on Advance TSMC Technology 28nm, 20nm.

Palo Alto, CA, US

Microprocessor Senior IC Layout Designer specialize in SRAM custom memory design.- Taped out many SPARC projects in production of 90nm, 65nm, 45nm technology.- Delivered L1 D-Cache block for SPARC microprocessor.- Delivered Memory Manageable Table Look Up Buffer for SPARC microprocessor.- Cadence VXL 6.1.5 Expert.- Mentor Graphics Calibre for LVS/DRC/ERC.

Milpitas, CA, US

• Senior Analog IC Mask Designer
• Fully responsible for eight different charge pump analog blocks.
• Floor plan & layout high voltage analog circuit using technique common centroid layout or ABBA technique to balance & minimize the differences in process of the two matching transistors.
• Understand thoroughly environment surrounding, how to prevent from latch up, resistance & capacitance related to layout.

IC Layout Designer- Delivered L0 & L1-Cache in.13um technology for MIPS Microprocessor. (Production Chip)- Delivered Phase Lock Loop (PLL) analog block in.15um technology for MIPS Microprocessor. - Delivered Dynamic 64 bit adder in.18um technology for MIPS Microprocessor (production chip)- Built standard & datapath library cells.- Chip level assembly.