Managing an FPGA IP Design Organization for Wireless Communication Segment and Highspeed Interconnect Segment.

Manage an IP design team of 40 engineers, and lead the development that cover a wide range of IP Portfolio: 5G (ORAN, eCPRI, CPRI, JESD204B/C), Highspeed Communication IPs (Serial Lite3/4, Interlaken) and Ethernet PTP 1588 IPs targeted for FPGA Implementation. Successfully lead the team to develop all these IPs to production, supporting new IP specification & features and supporting new generations of FPGA Devices. Also provide FPGA custom-design solution for leading Wireless & 5G Communication companies such as Ericsson, Nokia, Ciena, ZTE etc. Key Accomplishment:• Grow the IP engineering design team by 3X from 13 to 40 engineers.• Built new IPs competency: 5G IPs such as CPRI, eCPRI, ORAN, Comp/Decomp• Built new IP COE (Center of Excellence): Ethernet PTP 1588 IPs with 1.5ns accuracy. • Built FPGA Custom-Design Solution for major customers such as Ericsson, Ciena, Nokia & ZTE.

Responsible for the development & product release of Altera Ethernet IP & PTP 1588 IP Solution (co-own with US counterpart). Partner closely with US counterpart in product planning, development until the final phase of IP product release in Quartus. Develop the team competencies in relevant technical areas and aligning the employee’s career development plan with the team’s objective are also part of my daily tasks. Managed an IP Design team with a size of 13 engineers.Key Accomplishment:• Grow the IP Design Team from 6 to 13 engineers.• Built a few new FPGA IP competency:o 25G Ethernet IPo 2.5/5G Ethernet IP (NBASE-T, MGBASE-T)o PTP 1588 Time Synchronization IP

Pick up managerial role & own the development of Altera FPGA Ethernet IPs. Led the team of 6 to develop Altera FPGA Ethernet MAC & PHY IPs for 10M/100M/1G/10G. Key Accomplishments: • Build 10/100/1000Mbps TSE (Triple-Speed Ethernet) IP for Stratix V, Arria V & Cyclone V devices.• Build Low Latency 10M/100M/1G/10G (LL 10G) Ethernet IP.

Senior IP Design Engineer in Altera. Involved in the development & productization of Stratix V Serial Rapid IP (SRIO) 2.1 and XAUI PHY IP core in Quartus.Key Accomplishments:• Involved in the development of Serial Rapid IO (SRIO) 2.1 IP for Altera Stratix V Device.• Involved in the development of XAUI PHY IP for Altera Stratix V Device.

Emulation/Post-silicon SOC validation Lead in Embedded Communication Group (ECG), Intel Malaysia Penang. My job including come out with validation strategy, test plan, form execution plan and led the team to drive the end-to-end execution plan. Successfully led the validation of 2 “Adopt & Modify Platform” projects; eMenlow and Merom-Mukilteo2p with a project team of 3 engineers:Key Accomplishments:• Successfully caught the only silicon bug in eMenlow product line in its DDR3 Controller. Got the Divisional Recognition Award (DRA) by ECG for this achievement.

I started my career as a Silicon/Emulation Validation Engineer in Intel Network Processor Division. This including ~2 years of working experience in Intel Oregon, United States. Went through 2 project cycles of silicon validation in Intel System On-Chip. Specialized in Ethernet and System-On-Chip DFX Validation. Key Accomplishment:• Top RTL bugs finder in the validation team of 21 engineers in Intel Tolapai SOC program. Caught a total of 24 RTL bugs in the SOC; during my ~2 years assignment in Intel Oregon.