Tim Skelton Email and Phone Number

Designed a Ruggedized outdoor 1000W POE++ (IEEE 802.3bt) 80GB Cavium Octeon TX based Router system with high speed failover to 48V battery backup and integrated solar charger.

I produced Nella Terra's 2015 first harvest Estate Pinot Noir and Viognier wines.

Designed the Company's next generation IEEE 802.11ac CPE/AP currently being deployed. I was awarded US Patent No. 9,717,067 for this design.

Designed two DVT boards for the company’s next generation 802.11ac BBIC4 baseband IC.Supported the ASIC development team during all phases of board bring-up and SOC test.Performed validation and characterization of ASIC analog and digital I/O including 32bit DDR3, PCIe Gen2, SPI, RGMII, GPIO and PMU interfaces. Responsibilities included Compliance testing of all baseband SOC I/O.Wrote detailed documentation and application notes on AC/DC electrical characteristics, timing specifications and power consumption for datasheets, CoC and customer inquiries.Routinely participated in internal design review meetings for RDK system platform development.Review of customer’s schematic and PCB design layouts to ensure their success in meeting all development schedules and timelines.

Design and development of cutting edge high-performance Linux based network appliance platforms. Designed eighteen high-speed PCBA's including three 10 Gigabit Ethernet cards, 12-Port 10/100/1000 Ethernet, 6-Port fiber Gigabit Ethernet (SFF), 2-Port fiber Gigabit Ethernet (GBIC) and OC3, OC12, OC48, and OC192 cards all with failover bypass capability.Design and development of 22 layer high performance Freescale MPC8461D microprocessor based Applications Processor Card and RMI XLR Network Processor Card main system boards.PCIe design experience with LSI SAS controller and Cavium NITROX devices.Worked closely with CAD engineering group using 2D and 3D modeling tools for PCB layer stackup and high-speed differential channel design and layout.Worked closely with software and firmware development engineers for device register access and programming during board bring-up and system validation processes.Worked closely with mechanical engineers for component placement, thermal evaluation and cooling subsystems, EMI/EMC, faceplate and chassis design process issues.Responsible for design of all system DC-DC power supply circuits, power delivery systems, hardware RAID storage systems, management and console I/F's across three product platforms.Design and development of 500W and 735W N+1 hot-swappable -48VDC Telco PSU's for the B2000 and B7500 platforms footprint compatible and companion to Etasis EFRP-2603 2U system.Managed worldwide EMI/EMC and Safety regulatory compliance testing across all product platforms including UL, TUV, TUV Rheineland, CSA, FCC, CE and MET compliancy agencies.Engaged in next generation hardware development cycle utilizing current X86 multicore processor microarchitecture offerings from Intel Corporation.International travel for on-site engineering debug and positive resolution to system implementation issues experienced by high-profile customers.

Design of complex, high performance Microprocessor based communications equipment in a fast paced quick to market environment.Designs include implementation of OC3 and 10/100Mbit front end I/F's as well as QED RM7000A with level 3 cache and Galileo 64120 PCI Bus controller main system board.Assisted in development of ISDN POTS Port Office Router, PM3 and PM4 Remote Access Servers.Solved multiple stop-ship situations in a timely manner.

Co-Founder and Staff Engineer for a lucrative contract repair center. Duties included contract bidding, test setup and technical training.Responsibilities also included managing a team of 5 technicians.