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Tim Vogt is listed as Distinguished Engineer at Lattice Semiconductor, based in Hillsboro, Oregon, United States. AeroLeads shows a work email signal at latticesemi.com and a matched LinkedIn profile for Tim Vogt.
Tim Vogt previously worked as Distinguished Engineer at Sibeam, Inc. and Senior Software Manager at Sibeam, Inc.. Tim Vogt holds Msee, Electrical Engineering (Computer Architecture) from Purdue University.
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Creative HW/SW Architect and Problem Solver.Creative problem solver with experience in multiple technical domains who enjoys tackling complex problems and breaking them down into achievable solutions.Specialties: Hardware/software architecture, embedded software (C, C++, assembly), real-time software, RTOS, multithreaded design, Linux kernel drivers, SoCs and ASICs, software development methodology, software testing
Listed skills include Embedded Systems, Embedded Software, C, Soc, and 19 others.
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Hillsboro, Oregon, Us
Architecting FPGA silicon, software, and solutions. Driving strategic corporate technical initiatives, with areas of focus in FPGA configuration and security, embedded processing, and RISC-V. Defining technical requirements, writing specifications, and gathering data through research and modeling.
San Jose, Ca, Us
Responsible for software architecture and software development methodology for all 60GHz wireless products (WirelessHD video, WiGig/802.11ad, Snap wireless connectors, Project Soli micro-gesture recognition radar). Defined coding standard, code review methodology, and Linux device driver guidelines, and developed a low-memory debug logging system for use on for all wireless products. Designed, developed, and tested boot ROM for 802.11ad baseband chip. Developed device drivers (Android, Linux, Windows) and real-time embedded firmware (bare metal) for micro-gesture recognition radar sensor for the Google Soli project.
San Jose, Ca, Us
Built a high-performing 6-member software team from scratch to bring WirelessHD transmitter/receiver products to market after acquisition of SiBEAM. Came up to speed very quickly on large existing codebase (300K lines of embedded real-time code) with minimal documentation and no prior software team members. Dramatically improved code quality through major architectural improvements and a focus on continuous improvement through code cleanup and testing. Took three WirelessHD chips to production and supported customers through the design and production cycle. Came up to speed quickly on WirelessHD, 802.11ad, MA-USB, WDE, and USB3 protocols. Contributed to the corporate open source policy and approval process.
Managed a team of 4 software engineers developing embedded software for HDTV video decoder/video processor SoCs. Interfaced with remote teams to coordinate multi-site software development.Managed a team of 7 software engineers developing software to transport video and remote GUIs over TCP/IP (LiquidHD). Defined software architecture and design to implement the LiquidHD protocols. Architected and managed first software implementation of netCLIC network UI protocol. Made significant technical contributions to LiquidHD and netCLIC protocol specifications, which were intended to become open standards.Managed the company’s first ports of HDMI and MHL software to Linux kernel drivers. Managed real-time embedded software development for 10GbE video streaming technology demonstration. Established a common software development process to improve quality and consistency among software projects. Delivered complex software projects spanning multiple development sites (UK, Germany, China), on schedule and exceeding quality expectations. Managed local and remote teams.
Developed FPGA hardware platform, Windows software (C++, MFC), and test specification to test consumer electronics products for HDMI and HDCP compliance and interoperability (Simplay Labs certification). Defined software architecture and led software development team. Developed FPGA hardware platform including board design, logic design and verification (Verilog, Synplicity, Xilinx ISE), and USB firmware.Technical lead and project manager of a team of 3 software engineers for an HDTV decoder/video processor. Co-architected the software stack, wrote design specifications, and managed software development with a multi-site team (California, Taiwan, UK). Defined software development processes, methodologies, and coding standard for the multi-site software team.
Sunnyvale, California, Us
Developed multi-transport stream driver and firmware for the SupraHD (formerly TeraLogic) HDTV SoC and verified software and hardware in FPGA emulation and silicon. Architected and implemented a solution for generating partial transport streams for recording on IEEE1394 (Firewire) storage devices. Developed system-level tests for Operations to functionally screen chips. Provided remote and onsite customer support (Japan, California) and brought several key customers to production using Linux/RTAI and VxWorks.
Architected and implemented DVR software stack using MPEG transport streams, including partial transport recording and playback with full trick mode support. Developed MPEG transport demux firmware (assembly) and driver running on VxWorks and Linux/RTAI. Modified video and transport drivers to support trick mode streams from IEEE1394 storage devices (DVHS, AVHDD). Ported the Linux Trace Toolkit (LTT) to internal Linux development platform for HDTV decoders. Worked with the ASIC design team to architect multi-stream MPEG transport hardware for the Gen9 family of HDTV SoCs. Co-authored two patents related to this work.
Responsible for RTL, synthesis, and timing analysis of memory controller, video capture unit (CCIR-656), and PLL network in the TL850 HDTV decoder. Maintained top level RTL and testbench. Developed unit and chip-level regression tests for new features. Managed RTL releases and automated regression testing and generated test vectors for wafer sort. Brought up hardware acceleration platform (Quickturn) for pre-silicon verification. Architected and developed chip-level testbench in C, Verilog, and Tcl. Wrote testplans and created tests for chip-level verification. Developed a bug tracking system in Tcl/Tk which was used for many years.
Santa Clara, California, Us
Wrote assembly language tests to validate the Pentium and Itanium processors. Created innovative verification methods and developed software tools (C, C++) to automatically generate self-checking tests in assembly code. Some of these methods were subsequently disseminated corporate-wide as "best known methods" and earned two Divisional Awards and two Department Awards.Technical lead on several projects with 3-4 engineers, including development of software tools and methodologies. Developed structural cache tests for the Pentium processor in x86 assembly which dramatically improved detection of defects at wafer sort. Wrote testplans and assembly tests for the iA64 (Itanium) and iA32 (x86) instruction sets to validate microprocessor RTL models against behavioral reference models. Debugged failures down to the logic level in RTL simulation.
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Tim Vogt works for Lattice Semiconductor.
Tim Vogt is listed as Distinguished Engineer at Lattice Semiconductor.
AeroLeads has found 2 work email signals at @latticesemi.com for Tim Vogt at Lattice Semiconductor.
Tim Vogt is based in Hillsboro, Oregon, United States while working with Lattice Semiconductor.
Tim Vogt has worked for Lattice Semiconductor, Sibeam, Inc., Silicon Image, Zoran Corp., and Teralogic, Inc..
You can use AeroLeads to view verified contact signals for Tim Vogt at Lattice Semiconductor, including work email, phone, and LinkedIn data when available.
Tim Vogt holds Msee, Electrical Engineering (Computer Architecture) from Purdue University.
Tim Vogt is listed with skills including Embedded Systems, Embedded Software, C, Soc, Software Design, Device Drivers, Software Development, and Hardware Architecture.
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