Tim Ferrel Email & Phone Number

Mckinney, Tx, Us

Arlington, Va, Us

Utilized skills in electrical design/verification to verify, simulate, and document FPGA designs to protect the American war-fighter.• Created design models and corresponding simulations in Python/Cocotb that were used to verify functionality of FPGA designs built for defending U.S. Army soldiers operating tanks in combat situations.• Wrote and extensively documented detailed Verification Plan for scrutiny by greater design/verification team.• Deputy lead of Multi-Function-Radio-Frequency-System (MFRFS) Verification Team, and was frequently called upon to act for the lead during his absence.• Wrote Test Requirements Document and corresponding Master Test List for the Converged Electronics Stack of the Hit-To-Kill (HTK) Missile Project.• Graduate of Raytheon RiseUP Cohort V which is Raytheon financed preparatory training for program management. • Completed Raytheon Six Sigma Project.• Completed 12 week Raytheon ReLaunch Program.• Obtained U.S. DoD Secret Security Clearance.

• Completed engineering consultancy work on details of engineering design.• Retained currency in electrical engineering field through IEEE interaction and independent study.• Made Study of System Verilog.• Read Getting Started with UVM.

• VICE-CHAIR Institute of Electrical and Electronics Engineers (IEEE), Kansas City Section.• CHAIR IEEE Computer Society.• Liaison of the local chapter of the IEEE to the Joint Engineering Council of Kansas City.• Completed on-line courses and obtained certificates of completion in SystemVerilog and UVM. + Certificate URL’s = ude.my/UC-BO42X8V6 ude.my/UC-JMMNKH44 ude.my/UC-837H8IJ4• Seeking new opportunities to utilize my extensive electrical design/verification engineering expertise to work hard to achieve new innovative solutions in the world of high technology.

Chicago, Il, Us

• Held broad and detailed responsibilities in design/verification on projects for automotive stability control and anti-lock braking systems.• Coordinated Verification Process Review to ensure soundness of verification of the PEC3 SOC and drove action items to completion across greater design team.• Wrote headers and constructed self-checking tests in both master and slave modes in Verilog to verify the RTL and gate level design models of flash memory modules residing on an SOC.• Led verification efforts for the C3FR flash memory BIU and the PEC3 microcontroller.• Self-taught and utilized HDL Code Coverage tools to enhance verification quality.• Self-taught and utilized equivalency checking software to verify MCore microprocessor lakes of gates.• Acquired experience with both MCore and PowerPC microprocessors.

Austin, Texas, Us

• Provided needed verification expertise to the UC3F BIU flash memory verification effort.• Coded and submitted for review self-checking slave mode tests written in Verilog for the UC3F BIU flash module for the Spanish Oak project.• Assisted in porting over and massaging flash memory core tests for the Spanish Oak project.• Wrote and documented JAVA programs in house at Eureka to decode the machine language produced in personal check transactions into practical English.

Dallas, Tx, Us

• Member of greater design team that built industry's first cardbus controller• Held an array of design support responsibilities.• Coded self-checking tests in VHDL to verify bus solutions for PCI to PCI bridge and cardbus controller.• Gained expertise in the PCI signaling protocol.• Departmental fault grading champion with Sunrise fault simulation flow.• Fault graded PCI to 1394 Phy bridge chip.• Fault graded Cardbus controller and PCI to PCI bridge chips.• Gained experience in Synopsys design_analyzer, Synopsys test_compiler, Verilog, VHDL, Mentor QuickHDL/Quicksim, TI Design Support Software, Quickturn System Realizer emulation software, Signalscan, and C.• Gained familiarity with Cadence Verifault.

Dallas, Tx, Us

• Wrote testbenches in VHDL.• Generated timing analysis reports with the AIDA software application for the data processing unit of the vehicular management system of the F-22 military aircraft. Automated process with c-shell/awk scripts.

Msee, Electrical Engineering; Specialized In Computer Engineering Coursework

Bsee, Electrical Engineering

Ba, Computer Science And Physics (Double Major)