Timothy Tran Email & Phone Number

Milpitas, Ca, Us

Santa Clara, Ca, Us

• Successfully managed Design-Bid-Build and installed a MOCVD Aixtron reactor including Transfer Module, Abatement systems (Chlorine, Ammonia), Chiller, RF Generator, and other auxiliary support equipment. Obtained required permitting and passed varied city inspections• Perform in-house design and/or manage design-build efforts with external contractors or engineering consultants for tool installation of small to medium sized infrastructure projects• Hold design reviews with external design firms at various stages of the design and permitting process and identify value engineering opportunities. Determine best means of execution for various projects including design-build, or design-bid-build. Work closely with Automation, Environmental, and Safety Engineers on a variety of projects• Track infrastructure capacity including N+1. Support Operations & Maintenance team in troubleshooting and continuous improvement projects related to HVAC, Electrical, Mechanical and Plumbing. Provide budgetary estimates for prospective projects. Develop design scope and submits RFQ to design firms for a variety of facilities projects• Determine most cost-effective method form of bidding for given project including lump sum, GMP, or T&M NTE. Develop scope of work, bid documents, and hold contractor job walks to obtain competitive pricing for a variety of facilities projects including Fab and building architectural, mechanical, electrical, and process piping (MEP) projects• Manage selected contractor’s activities. Ensure adherence to safety standards, code compliance, workmanship, materials selection, adherence to site standard specifications, and quality. Review and respond to submittals and RFI’s• Develop high level project timelines, Gantt charts, etc. to track and insure timely execution of projects. Track budget and spending and inputs into database. Generate purchase requisitions. Perform project punch-list, closeout , as-built documentation, etc.

• Managed construction of varied facilities/infrastructure related projects supporting Apps Lab in Buildings 81 & 85 at AMAT.• Successfully completed construction of minor and major facilities infrastructure e.g. Upgraded Solvent Exhaust, FICW system, PCW system; Replaced sanitary sewer line; Installed new equipment in Athena Lab, SFEM FI module, PN2 gas lines etc.• Installed and/or removed semiconductor processing tools in R&D facilities e.g. chamber, FI, pump, chiller, gas lines, etc.• Supported moderate building facilities activities including, but not limited to, expansions, consolidations, and improvements.• Performed detailed coordination of construction: Obtain construction bids from approved suppliers; Develop budget; Obtain permits; Develop appropriate Purchase Requisitions; Coordinate construction activities; Coordinate and attend safety walkthroughs and city inspections; Assist in monitoring vendors for safety compliance, project performance, and schedule performance; Ensure all project schedules meeting customer commitment; Perform all associated pre- and post-project documentation and closure activities; Other responsibilities as assigned by the employer and/or the client.

Fremont, Ca, Us

- Worked in fast-paced R&D (Advanced Technology Development Group)- Successfully developed novel SCD/ALE PR treatment for EUV patterning to improve LCDU (Local CD Uniformity) to <1.4nm 3σ in both ICP (Kiyo EX) and CCP (Flex GL) tools through Lam/ASML JDP. Applied to TSMC N5 via demo on Flex GL and achieved 1.5nm 3σ LCDU. Co-authored in published paper. - Worked with team to develop low cost multi-patterning (SADP/SAQP) Metal Oxide Spacer on Spacer with PR Mandrel for Memory application on Conductor etcher and transferring to customer site. Collaborated closely with Productivity to develop WAC to meet customer metal contamination specification - Supported Deposition Product Group in Velocity Lab utilizing CPM (Coupon Process Module) to develop SiN ALD in ICP source evaluating 3 different precursors 2nTe (amide), Si2H6, Viper (halide) - Performed demos on varied TSMC N3/N5 applications e.g. SOC, ZrO2, Inpria EUV PR

Fremont, Ca, Us

- Leading etch process engineer responsible for all CIC (Customer Integration Center) projects pertaining to etching (DE: Flex EL/FL, CE: Kiyo EX, TSV: Syndion-C)- Developing QPT process using a-Si Core to provide advanced structures to internal BUs- Successfully developed Spacer based (TiO2) patterning scheme through QPT for 11nm half pitch with <1.5nm 3σ CDU in carbon mask layer. - Enabled EUV lithography with thin resist and improved local CDU. Developed HM and etch processes to deliver <2.5nm local CDU @ 52nm pitch for hole and cut masks with 60-80% shrink from resist to target layer.- Achieved patterning of high AR ≥ 20:1 through DPT in Silicon through use of Oxide HM - Successfully developed a DPT etch process (22nm half pitch) on Silicon target layer with Empire II mask (Granular pattern). Running limited production on a regular basis to supply to internal customers.- Successfully developed an M1 etch process with CNSE Empire-II mask on Flex EL- Provided etch expertise and support to integration projects within CIC and other Product Groups

Fremont, Ca, Us

- Responsible for real time process monitoring of all deposition tools (Cu-In-Ga-Se absorber layer), data analysis, improvements to yield, and tool uptime performance- Worked closely with Engineering/Maintenance groups to identify and resolve hardware/software issues; Evaluated new hardware and monitoring controls to drive product/reliability improvements

Fremont, Ca, Us

- Customer Technologist Manager (CTM) – Managed UMC etch process technology by actively engaging with customer engineers and local process team to improve existing processes in cost of ownership (COO), yield enhancement, throughput improvement, hardware testing, and collaborated in qualifying new applications- Performed demo projects in R&D lab and at customer sites in both Conductor and Dielectric etch- Supported various international local field accounts to resolve escalations related to hardware, process, failure analysis, and integration issues to gain market share and customer trust- Experienced with Lam Reliant Conductor and Dielectric etch products- Supported global customer base in development and technology transfer by frequent travel

Phoenix, Arizona, Us

Plasma Etch Process Engineer- Responsible for Oxide etch module overseeing 12 Lam 4520 Oxide etch systems in Class 1 CMOS/BiCMOS Fab- Optimized and monitored critical process parameters utilizing SPC, DOE, FMEA, Lam Station. Set up automation to prevent/eliminate misprocessing. Wrote and trained operators on SOP.- Led a task force of engineering technicians and lead operators in determining root cause of misprocessed lots. Established corrective actions and wrote 8D report closure- Performed cross-functional projects to improve existing products’ cycle time, cost reduction, SPC, yield, equipment utilization- Worked closely with R&D team to develop etch processes for new products- Worked with Integration engineers to improve parametric yield, final yield, reliability etc.- Sustained Poly & Nitride etch applications on Lam 4420 etchers and Photolithography module

Ms, Electrical Engineering

Bs, Microelectronics Engineering