Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

I taught Geometry, Algebra, and Pre-Algebra.

Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

I taught 7th grade math and science classes.

Provided substitute teaching services in the middle school of the Santa Clara Unified School District.

Worked as a substitute teacher for August Boegart Middle School.

Provide educational services for the school district, enabling teachers and other professional educators time to catch up, attend meetings or training, get away, or recuperate.

Provide Engineering support for CAE software used indesigning IC's. Work with engineers and vendors to solveissues with the software and designs.

Certified in the ITIL Foundation IT-Service Management. Worked with the ITIL Process managers to review, test, document, and approve software releases in order to maintain a consistant and error free working environment.

Worked on an Apple Computer project, coordinating design work between the Technology Center and customer engineers.Worked for the Technology Center Department as part of the ASIC Design Support Group, providing tool and design debug support.Provided Physical Verification (DRC, LVS) for designs using Avanti Hercules and Mentor Calibre, Debugged IC prototype using FIB and other diagnostic tools. Evaluated new tools, such as Cadence’s Silicon Ensemble for the IC… Show more Worked on an Apple Computer project, coordinating design work between the Technology Center and customer engineers.Worked for the Technology Center Department as part of the ASIC Design Support Group, providing tool and design debug support.Provided Physical Verification (DRC, LVS) for designs using Avanti Hercules and Mentor Calibre, Debugged IC prototype using FIB and other diagnostic tools. Evaluated new tools, such as Cadence’s Silicon Ensemble for the IC Design Flow migration from the older flow which used Compass Design Automation.Worked on developing and distributing the TC’s standard design environment to local and international sites by replicating the core design tools. Provided a common setup that all engineers could use, no matter which site they were working from. Show less

Worked on the Apple Computer Team to design several IC designs using Compass Design Automation tools. Was responsible for floorplanning, pad placement, analog signal routing, clock and power routing, package configuration, physical verification(DRC,LVS), timing extraction, prototype debugging, and design environment configuration.

Provided pre- and post-sales technical support for marketing department. Wrote application notes and design manuals to help customers with their circuits.Designed simulation library for ECL Technology.Worked on Siemen's SABC501 microprocessor, using Cadence's Tancell tool to place and route blocks and the top level design. Also used Mentor's CAECO Layout Editor to do manual edits of the physical layout.Used Cadence's Gate Ensemble software to place and route ECL and CMOS gate… Show more Provided pre- and post-sales technical support for marketing department. Wrote application notes and design manuals to help customers with their circuits.Designed simulation library for ECL Technology.Worked on Siemen's SABC501 microprocessor, using Cadence's Tancell tool to place and route blocks and the top level design. Also used Mentor's CAECO Layout Editor to do manual edits of the physical layout.Used Cadence's Gate Ensemble software to place and route ECL and CMOS gate array designs. Used Dracula software to do LVS, ERC, DRC checks.Debugged IC prototypes using probe stations, oscilloscopes and other diagnostic tools. Show less

Converted a 5 chip design from one ASIC foundry process to another, simulating and correcting timing and functional errors.Worked on multiple ASIC Designs, providing schematic entry, simulation, test vector generation, and tapeout documentation.Provided system administration support for design staff on design entry systems.

Reviewed customer schematics for possible ASIC gate array design.Responsible for design conversion, circuit simulation, macrocell creation, schematic entry, netlist generation and library development.Responsible for prototype debugging.Automated design flow by scripting common steps used for netlist creation.