Tim Swensen Email & Phone Number

Santa Clara, Ca, Us

Plano, Texas, Us

Driving performance iniatives for AFS XT and Solido SPICE, the Siemens circuit simulators. Serving as the technical expert in customer engagements. Demonstrating the value of our EDA tools to customer success.

Plano, Texas, Us

Product Engineer in Circuit Simulation team. Driving improvements in AFS (SPICE) Simulator for our customers. (This is a continuation of my role at Mentor, which was acquired by Siemens.)

Wilsonville, Or, Us

Product engineering for Mentor Graphics AFS and AFS Mega. Specializing in embedded SRAM characterization.

FPGA Configuration and Security• Designed and managed layout for a non-volatile fuse block and AES battery-based key register block for FPGA configuration engine in 20nm process.• Designed, managed layout, wrote test procedure, and carried to tapeout a non-volatile metal fuse test chip in 20nm process. Achieved first-silicon operational success.• Consulted with CAD to develop power domain verification methodology in a multi-supply FPGA using Mentor PERC. Verified power domain integrity of configuration subsystem using this tool.• Verified logical equivalence of RTL Verilog models and custom IP block schematics using Cadence Conformal LEC formal verification tool.• Verified proper coding style and syntax in block level RTL models using Spyglass lint tool.• Performed static timing analysis on volatile and non-volatile fuse blocks using NanoTime.• Ensured timing closure of programming control and Design-for-Testability circuitry.• Interfaced with US Government agencies and DoD contractors to ensure FPGA design security against attack vectors.

Hillsboro, Oregon, Us

FPGA Embedded SRAM, Configuration, Routing Fabric• Designed sense amp, bit line mux, write drivers, output mux and address decoder logic for embedded SRAM blocks within FPGA products. Designed down through 65nm process.• Supervised layout designers in physical design of components for embedded SRAM blocks.• Developed SRAM functional test and speed characterization patterns for use in production.• Verified interface logic between full chip programming circuitry and SRAM block to ensure proper operation of SRAM pre-load and read-back, using Verilog test bench that I developed.• Wrote and verified Verilog behavioral model of entire embedded SRAM block for 65nm FPGA.• Invented a technique for eliminating glitches in SRAM output decoder by exploiting the decoder architecture to feedback existing outputs prior to address transition. US Patent #7,149,129• Invented circuitry for doubling of SRAM data width in pseudo-dual-port mode without doubling the number of write drivers and sense amps. US Patent #7,539,076• Invented an architectural technique for pre-loading all unused, latched routing mux outputs in an FPGA fabric through a novel arrangement of mux control bits in the address space, eliminating floating nodes without adding a pre-load transistor to each mux. US Patent #7,663,401• Invented a circuit topology to ensure limited bit line voltage swing in a dual-port SRAM, reducing the effect of opposite-port operations on read speed. US Patent #8,451,679

West Lafayette, In, Us

Classroom teaching assistant in EE and Mathematics departments.Graded exams, held office hours, lectured, assigned grades(lectured and assigned grades in math dept. courses only).

Munich, De

Medical diagnostic ultrasound systems. Company was later acquired by Siemens.• Designed test fixtures and automated test software for signal processing circuit boards in medical ultrasound scanner.• Deployed test systems on production floor. Systems used a combination of custom hardware and commercial test instruments under IEEE-488 bus control.• Wrote test specifications and test procedures for signal processing circuit boards.• Trained technicians in circuit test and debug.• Led manufacturing debug efforts for production failures and signal integrity problems.

Msee, Electrical Engineering

Bse, Engineering -- Electrical Concentration

Electrical Engineering