Vp Of Engineering
CurrentManage analog and mixed-signal design teamLead high performance SerDes IC product development
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@norelsys.com
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Ting Wu is listed as VP of Engineering at Norel Systems at Norel Systems, a with 4 employees, based in Fremont, California, United States. AeroLeads shows a work email signal at norelsys.com and a matched LinkedIn profile for Ting Wu.
Ting Wu previously worked as VP of Engineering at Norel Systems and Engineering Director Analog IC Design at Norel Systems Ltd.. Ting Wu holds Ph.D., Electrical Engineering from Oregon State University.
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Ting Wu is a VP of Engineering at Norel Systems at Norel Systems. They possess expertise in mixed signal, ic, circuit design, pll, integrated circuit design and 11 more skills.
Listed skills include Mixed Signal, Ic, Circuit Design, Pll, and 12 others.
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Manage analog and mixed-signal design teamLead high performance SerDes IC product development
Responsible for development of high performance PLL, low power clocking, and high speed signaling. Selected publications: • F. Aryanfar, T. Wu, M. Koochakzadeh, C. Werner, and K. Chang, “A sub-resonant 40GHz clock distribution network with near zero skew,” IEEE International Microwave Symposium (IMS), May, 2010. • T. Wu, F. Aryanfar, H. Lee, J. Shen, T. Chin, C. Werner, and K. Chang, “Low skew clock distribution using zero phase clock buffer DLLs,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 176-177, Feb. 2010. • K. Chang, T. Wu, K. Kaviani, and J. Chun, “SOI design for a high-performance IO interface (Invited)”, IEEE International SOI Conference, pp. 1-4, Oct. 2009. • H. Lee, K. Chang, J. Chun, T. Wu, Y. Frans, B. Leibowitz, N. Nguyen, T.J. Chin, K. Kaviani, J. Shen, X. Shi, W. Beyene, S. Li, R. Navid, M. Aleksic, F. S. Lee, F. Quan, J. Zerbe, R. Perego, and F. Assaderaghi, “A 16Gb/s/link, 64 GB/s bidirectional asymmetric memory interface”, IEEE Journal of Solid-State Circuits, pp. 1235-1247, Apr. 2009.• T. Wu, X. Shi, K. Kaviani, H. Lee, J. Chun, T. Chin, J. Shen, R. Perego, and K. Chang, “Clocking circuits for a 16Gb/s memory interface”, IEEE Custom Integrated Circuits Conference (CICC), pp. 435-438, Sep. 2008.
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Dissertation titled "Design Techniques for PVT Tolerant Phase-Locked Loop". Won the Best in Session Award (Circuit Design Session).
Pioneered a pipeline architecture for a large crossbar switch fabric chip. Presented in Hotchips 2002, which was reported by EETimes.
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Ting Wu works for Norel Systems.
Ting Wu is listed as VP of Engineering at Norel Systems at Norel Systems.
AeroLeads has found 1 work email signal at @norelsys.com for Ting Wu at Norel Systems.
Ting Wu is based in Fremont, California, United States while working with Norel Systems.
Ting Wu has worked for Norel Systems, Norel Systems Ltd., Rambus, Broadcom, and Via Tech..
Ting Wu's colleagues at Norel Systems include Walter Wang, Wei Cao, and Matt Trobowsky.
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Ting Wu holds Ph.D., Electrical Engineering from Oregon State University.
Ting Wu is listed with skills including Mixed Signal, Ic, Circuit Design, Pll, Integrated Circuit Design, Cmos, Analog, and Analog Circuit Design.
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