T. M. Mak Email & Phone Number

San Jose

Test Methodologies, system design and integration

Union City, Ca

Santa Clara, Ca

Developed test strategies for various foundry products, especially with complex fab/assembly processes, e.g. 2.5/3D. Worked with test development teams to formulate price quotes. Assisted Sales team to explain/communicate to customers about quotes and test requirements. Developed KGD new test business initiative.

Santa Clara, Ca

Developed test strategies for advanced 2.5 / 3D assembly technologies.* Proposed novel test and debug methods for Silicon Interposer, ensuring each were low cost and HVM compatible. Worked with customers and OSAT, implementing suggested strategy. Worked with partners and collaborators on test features in advanced test vehicles. * Defined similar test strategy for 3D die stacking. * Developed cost model, illustrating how more testing actually would save cost on final module; cost ROI… Show more Developed test strategies for advanced 2.5 / 3D assembly technologies.* Proposed novel test and debug methods for Silicon Interposer, ensuring each were low cost and HVM compatible. Worked with customers and OSAT, implementing suggested strategy. Worked with partners and collaborators on test features in advanced test vehicles. * Defined similar test strategy for 3D die stacking. * Developed cost model, illustrating how more testing actually would save cost on final module; cost ROI is 10 to 1.* Filed 3 patents on various packaging innovations. Show less

Responsible for test technology development, e.g. HSIO test, MEMS self test, RF self test, test for TSV die stacking, embedded DRAM test.

manager responsible for test methodology development

Identified long term industrial challenges. Disseminated trends and visions via numerous presentations at partner schools. Coached research students on their researches.

Santa Clara

Developed AC IO loopback test methodology for Source Synchronous IO and HSIO. Co-chaired corporate level team meeting to drive this into a "Best Known Methodology". Chaired corporate level team meeting to drive cache DFT, e.g. Direct Access Test methodology for large embedded caches.Developed DFT to allow component self test with proper bus cycle hand-shaking.Drove scan layout methodologies to allow efficient DFT layout for custom datapath and layout synthesis.Mentored and… Show more Developed AC IO loopback test methodology for Source Synchronous IO and HSIO. Co-chaired corporate level team meeting to drive this into a "Best Known Methodology". Chaired corporate level team meeting to drive cache DFT, e.g. Direct Access Test methodology for large embedded caches.Developed DFT to allow component self test with proper bus cycle hand-shaking.Drove scan layout methodologies to allow efficient DFT layout for custom datapath and layout synthesis.Mentored and transferred various academic research into internally design and CAD capabilities. Show less

drove methodology convergence among different processor design teams. Project received D2000 award later.

Managed ASIC CAD and computing resources (budget of over a million dollars); Provided CAD tool support for 2 projects (3 chip design teams).

responsible for Product Engineering for M286, C286 kit, PC Kit, 80386SX peripheral chip. Recruit/build a PE team to develop manufacturing and silicon debug capabilities for 80386SL and 80486SL. Champion DFT and DFM for this product family.

responsible for bringing 80286 peripherals to the market.

Hong Kong And Sf Bay Area

Ran test factory; tested bare die on PCB; Set up probe card build and repair operation; Ran the whole supply line from US to wafer fab in HK .

My first test job, on single transistor. I know how to get VI from a curve tracer (and know how to intepret the image). I programmed transistor tester with thumb switches and paper tapes.

High Diploma, Equivalent To Bsee, Electronic Engineering

Education record