GPU, System IP and SoC architecture engineering program management. Focused on the successful on time delivery of the IP roadmap achieving performance and quality objectives. Developing project plans and managing engineering teams through scheduling, resourcing plans, risk management, quality and performance metrics. Partnering with global engineering teams to integrate IP into SoCs for mobile, automotive and custom silicon solutions.

Manage product engineering function for SoC's product development cycle with direct and virtual reports. Lead team in defining design productization features, post silicon validation, test content and strategy, executing to achieve quality goals, and setting individual parts specifications for best performance.- Notable product introductions: AMD Kaveri APU, Brazos 1st APU to market delivered in record time to market.

Served as lead technical engineer on projects responsible for validating product specifications, debugging to increase product frequency, and setting product definition. Developed and executed project plan while technically mentoring other engineers.- Guided virtual team of design, platform design, and product team contributors and analog circuit validation lead.- Developed world's first x86 64 bit processor with first on-board memory controller by managing and developing detailed analog IO strategy and silicon verification plan while containing leading-edge transistor technology changes to mitigate risk.- Developed first 1 GHz processor through vigorous speed debug in conjunction with design and fab's transistor technology, further demonstrating industry-leading technical skillsets and performance.

Acted as DFT feature, HDL, verification, and implementation engineer.- Led new custom memory BIST control capability and implementation / verification into existing BIST controller, providing more flexible read / write algorithms that enabled better coverage against industry's flexible means of memory access.- Completed AMD first fuse controller HDL, implementation and full verification, allowing configurable processors to match individual market needs and saving on mask cost and supply infrastructure complexity.- Guaranteed high-performance and bug-free first design tapeout through integration and verification of analog IO into full chip-level design.

Responsible for post-silicon validation of new CPU product introductions

AMD Fab 10 product engineering responsible for test and yield debug of non-volatile memory products.AMD CPU product line engineering responsible for design validation and test of the K5/K6 CPU.