Tom Joyner
AeroLeads people directory · profile

Tom Joyner Email & Phone Number

Sr. Semiconductor Packaging Engineer at Self- Employed Multidisciplined Engineer
Location: Greater Pittsburgh Region, United States 6 work roles 1 school
LinkedIn matched
✓ Verified July 2026 3 data sources Profile completeness 100%

Contact Signals

LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Self- Employed Multidisciplined Engineer
Role
Sr. Semiconductor Packaging Engineer
Location
Greater Pittsburgh Region, United States

Who is Tom Joyner? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Tom Joyner is listed as Sr. Semiconductor Packaging Engineer at Self- Employed Multidisciplined Engineer, based in Greater Pittsburgh Region, United States. AeroLeads shows a matched LinkedIn profile for Tom Joyner.

Tom Joyner previously worked as Sr. Packaging Engineer at Teledyne Imaging Sensors and Sr Packaging Engineer at Intel. Tom Joyner studied at United States Air Force Technical Training Center Chanute Afb Illinois.

Profile bio

About Tom Joyner

Tom Joyner is a Sr. Semiconductor Packaging Engineer at Self- Employed Multidisciplined Engineer. He possess expertise in semiconductors, manufacturing, electronics, sensors, design of experiments and 45 more skills.

Listed skills include Semiconductors, Manufacturing, Electronics, Sensors, and 46 others.

Current workplace

Tom Joyner's current company

Company context helps verify the profile and gives searchers a useful next step.

Self- Employed Multidisciplined Engineer
Self- Employed Multidisciplined Engineer
Sr. Semiconductor Packaging Engineer
6 roles · 37 years

Tom Joyner work experience

A career timeline built from the work history available for this profile.

Sr. Semiconductor Packaging Engineer

Current
Self- Employed Multidisciplined Engineer

Derry, Pennsylvania

A Semiconductor Packaging Engineer with over 15 years of experience in manufacturing process development, mechanical package design and subcontract assembly management.•16 years custom electronic packaging and tactical dewar design of which 9 years for Infrared Focal Plane Arrays operating at cryogenic through room temperatures.• 23 years’ experience in assembly process engineering of hermetic and plastic semiconductor assemblies.• Experience in assembling to MIL-STD 883, MIL-M-38510, MIL-PRF-38534.• Experience includes Class S, Class K and Commercial hermetic assembly.• Experience in assembly related failure analysis of semiconductor components.• Computer literacy in Microsoft DOS and Windows OS’s, Microsoft Office Suite (Visio, Project, etc.), AutoCAD 2D and SolidWorks 3D modeling.• Experienced in the use of Design of Experiments (DOE’S) and Statistical Process Control (SPC).• Experience in electronics component level troubleshooting of automation and electronics equipment.• Active Security Clearance

Jun 2013 - Present

Sr. Packaging Engineer

Teledyne Imaging Sensors

Packaging engineering team lead consisting of 3D designers, drafters and thermal mechanical analyst. Providing program package design to the customer’s physical, environmental and electrical requirements. Using SolidWorks, AutoCAD, Analytical software.Interface between packaging team and other program team members. Providing FPA, C-MOS design engineers, Camera, Test and marketing personnel with suitable packaging solutions for current and future programs.Provide technical analysis to designers, Quality assurance, Production and Test personnel.Required to develop conceptual proposal models and budgetary costs on program packaging for marketing proposals.Technical liaison between TIS and subcontract assembly facilities or suppliers.Provide in house technical support regarding assembly related issues. Assist in Debugging of development and applications test boards.Custom design, development and selection of product development fixtures and shipping material.Failure analysis interpretation of design and assembly related defects.Required to write operations specifications to provide procedures for device sampling and shipping processes.

Jul 2003 - Jun 2013

Sr Packaging Engineer

Provide design engineers and marketing personnel with suitable packaging solutions for current and future products. Perform device/package development duties and provide technical analysis to designers, Quality assurance and production test personnel. Reduction of subcontract cycle time for engineering and product development devices. Technical liaison between subcontract assembly facilities and Intel, and between Intel Calabasas Design Center and Intel Sacramento. Provide in house technical support regarding assembly related issues. Assist in Debugging of development and applications test boards. Custom design, development and selection of product development fixtures, JEDEC trays, waffle packs, shipping tubes. Failure analysis interpretation of assembly related defects. Required to write operations specifications to provide procedures for device sampling and shipping processes. Produce AutoCAD wire bond drawings, package outline drawings

2001 - 2003 ~2 yrs

Subcontract Assembly Managment

Identify and qualify new subcontract assembly facilities. Reduction of subcontract cycle time by automation and process refinement. Liaison between subcontract assembly facilities, material suppliers and Vitesse. Provide in house technical support regarding assembly related issues. Identify Incoming requirements and inspection criteria of raw material and package piece parts. Custom design and development of product handling fixtures, JEDEC trays, waffle packs, shipping tubes, die attach and welding equipment components using AutoCAD. Operator and maintenance personnel training in the use of computer controlled optical inspection systems and lead scan equipment. Failure analysis interpretation of assembly related defects. In-house support for post test assembly related processing. Required to write production specifications, maintenance specifications, initiate engineering change notices, and formal reports. Produce AutoCAD wire bond drawings. Produce package outline drawings. Design of metal glass packages for laser drivers. Perform device/package development duties and provide technical analysis to designers.

1997 - 2001 ~4 yrs

Associate Engineer

Alphatec (Aka Indy Electronics, Olin Interconnect)

Production process development for new product and optimization of current processes using process capability studies, design of experiments, and statistical process control methods. Process sustaining engineer responsible for both furnace sealing and parallel seam welding, product marking using both offset and pad printing systems, lead trim, solder lead finishing using static dip bath, wave solder equipment and MECO plating systems, temperature cycling, constant acceleration, particle impact noise detection, hermetic testing using Kr-85/ helium fine leak testing and bubbler/ vapor perflorocarbon gross leak testing, burn-in, stabilization bake, lead inspection using RVSI 2700/3900 lead inspection systems, external visual of ceramic, plastic, and M-quad semiconductor devices to MIL-STD-883D and MIL-38510 requirements. Required to write production specifications, maintenance specifications, initiate engineering change notices, and formal reports. Required to perform failure analysis of product using Zyglo and Red die penetrant testing and interpretation of Electron Dispersive Spectrometer and Scanning Electron Microscope analysis. Design equipment subassemblies and modify equipment for greater productivity and quality upgrading. Perform maintenance actions on manufacturing equipment to include conveyor and standard convection and infrared ovens, burn-in ovens, thermal shock chambers, pressurized test vessels, constant acceleration testing equipment (centrifuge), offset and pad printing equipment, digital controllers, acid precleaning equipment, wave and static solder equipment, hydraulic and pneumatic presses, magnetizing, automated plating equipment.

1990 - 1997 ~7 yrs

Staff Sargent

Castle Afb California And Fairchild Afb Washington

NCOIC Munitions Maintenance Varification and Checkout Equipment Shop (VACE)

Dec 1980 - Jan 1990
1 education record

Tom Joyner education

  • United States Air Force Technical Training Center Chanute Afb Illinois
    United States Air Force Technical Training Center Chanute Afb Illinois
FAQ

Frequently asked questions about Tom Joyner

Quick answers generated from the profile data available on this page.

What company does Tom Joyner work for?

Tom Joyner works for Self- Employed Multidisciplined Engineer.

What is Tom Joyner's role at Self- Employed Multidisciplined Engineer?

Tom Joyner is listed as Sr. Semiconductor Packaging Engineer at Self- Employed Multidisciplined Engineer.

Where is Tom Joyner based?

Tom Joyner is based in Greater Pittsburgh Region, United States while working with Self- Employed Multidisciplined Engineer.

What companies has Tom Joyner worked for?

Tom Joyner has worked for Self- Employed Multidisciplined Engineer, Teledyne Imaging Sensors, Intel, Vitesse Semiconductor, and Alphatec (Aka Indy Electronics, Olin Interconnect).

How can I contact Tom Joyner?

You can use AeroLeads to view verified contact signals for Tom Joyner at Self- Employed Multidisciplined Engineer, including work email, phone, and LinkedIn data when available.

What schools did Tom Joyner attend?

Tom Joyner studied at United States Air Force Technical Training Center Chanute Afb Illinois.

What skills is Tom Joyner known for?

Tom Joyner is listed with skills including Semiconductors, Manufacturing, Electronics, Sensors, Design Of Experiments, Materials, Spc, and Pcb Design.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.

People with similar names

Check these profiles if this is not the Tom Joyner you were looking for.

View similar profiles