Tom Stader Email & Phone Number

Santa Clara, California, Us

Program Implementation Manager on the Product Engineering Team for “state of the art”, Enterprise Server products. Responsibilities are defining and managing key product deliverables/schedules and driving cross functional activities. Responsible for pre-silicon planning and once silicon arrives, will drive customer samples execution and high volume manufacturing readiness. Manages horizontally across several functional organizations is a key job function. The role requires working hand-in-hand with our Asia Engineering and Operations counterparts, extensive interactions within the Product Engineering organization, and interacting with several other internal organizations (Design, Supply Chain, Business and Customer Engineering).

Santa Clara, California, Us

Supervised and coordinated the activities of Platform Validation personnel to ensure projects were completed on time, on budget, and as specified. Recent results were a flawless power-on support for one of Intel’s flagship products.Lead and managed a space saving effort to improve the efficiency of our laboratories. We were able to save $450k as well as increase the lab capacity by twice the original capacity.Directly managed a multi-national team through 9 product launches with a 30% increase in efficiency.Improved the engineering team’s customer scores by 23% from the previous years.Improved scheduling of R&D Client work and engineering time across two labs (Oregon and Costa Rica) and improved availability by over 5% a savings of $~1.5 million.Received a Division Level Award for establishing a single process to review the overall performance of Client products supported by global teams. Coordinated new software tools that increased the efficiency and communications across multiple teams. Successfully installed over 80% (over 3000 systems) of our systems world-wide as well as documenting the process for future support.

Santa Clara, California, Us

Received 3 Division level recognitions for Reduced Time-to-Market for Intel’s Xeon Server products, as well managing silicon milestones for multiple Intel product lines.Worked with Product Engineering teams to increase capacity and predictability with regards to schedules. Received recognition from PDE teams for getting Samples out in record setting time. Led teams (PDE, Qual, MFG) through daily, weekly and monthly meetings to coordinate and provide focus on silicon issues needing resolution. This was done from Tape-In to Launch across multiple labs and geos.Successfully launched Intel’s E7505 chipset, this included managing headcount and resources necessary to be ready for 1st silicon. Received an “A” Post Mortem Grade of 3.9 out of 4.0.Tracked Intel’s Xeon E5-2600 CPU (Jaketown) program readiness (1000+ line items) and communicated program status to all levels of management, as well as drove mitigation plans to make sure there were no impacts to schedules and product deliveries. Significantly enhanced Intel’s revenue and success with outstanding program management execution for material run in SVC. Reduced qualification time for OEM delivery by over 30%.Influenced and deployed web-enabled tools for project planning, as well as real-time tracking that allowed for products to be run with 50% less headcount per year.Worked Capacity and Throughput calculations, involved PDE team(s) to make sure all needs and potential milestones were met. This was evidenced by an execution score of 97%. Also received outstanding remarks for support of aggressive and difficult Server Qualifications.Recognized for a difficult Qualification process for multiple products (Pentium 4 and Itanium). This also involved meeting 48 hour commitments and managing Customer Fallout (CLF) units.

Introduced innovative Engineering and Operational changes to improve product reliability and manufacturability. Modeled operational capacity and output for entire organization. Also, was responsible for all activities with respect to ISO 9000/9001 to ensure engineering compliance and certification. Improved equipment and operational utilization by over 10%, consequently increasing output and decreasing costs by over $8 million.Established software systems to handle inventory, product disposition, scrap and other quality issues. Failure rates dropped from 35% to less than 1%, a savings of over $150,000 per month.Project Manager for multiple new product introductions (16 Meg DRAM, 64Meg DRAM, and 128 MEG DRAM).Implemented a Test reclaim process, resulting in savings of over $1.2 million/year.Granted "Leadership Achievement Award" by President of the Company.Responsible for Test Engineering ISO 9001 certification. Received a "perfect score" by auditors, one of the best ratings in the company.

Santa Clara, California, Us

Responsible for the operations and control of product at Intel's FAB 9/11 Test facility. Job responsibilities included making sure schedules were met, controlling the flow of material. Ensured direct reports and shift managers are responding to correct priorities in line with business needs. Consistently rated in the top of my peer group.Used an understanding of Test systems, Production controls, and modeling theories to reduce testing rates from 50% to 5%.Improved operations in the Test area, this change resulted in a 3% increase in productivity saving many thousands of dollars.Received Intel awards for outstanding work in leading and ramping the FLASH and Pentium product lines at Intel.

Fayetteville, Ar, Us

Published in the American Society of Civil Engineers as a graduate student for my Master's Thesis.

Arlington, Virginia, Us

US Combat Veteran awarded two Bronze Stars for superior leadership and performance during Desert Storm/Shield.

Bs, Mathematics Sciences

Ms, Operations Research 3.67/4.0