I am an award winning integration engineer who has extensive experience with leading all of the process modules to meet defect, yield, & reliability requirements for Intel's state of the art Semiconductor process for 14nm, 22nm, 32nm, & 45nmI have Led Technology transfers from R & D into Manufacturing for Intel's world wide factories. I have developed and taught new process development courses to all factory staff to assist in the rapid introduction of the new semiconductor processes. I have been the Team lead for the 1st process transfer to a non CE! virtual factory.This entailed learning a completely new process, introduction of Copper materials into the metallization of the process, defining and communicating the required protocol to ensure no cross contamination, & leading the education for the home fabrication facilityThis highly successful transfer enabled rapid volume ramp in the new factory in record time.I have developed new SPC methodologies to prioritize the largest areas of instability & then worked with various process engineering groups to identify & eliminate significant number of Lithography, Metrology, Etch & CMP constraints. To support these efforts I created new DOE methods for analyzing these state of the art processes.I have been the Focus Team chair which is responsible for technical assessment & approval for all process changes in the Contact module.I have screened, interviewed, hired and trained a completely new staff for a Die to mother board interconnect system. All of this was performed under an exceptional tight timeline. I have led factory wide defect teams to identify and eliminate large sources of contamination.

Managed Yield department inclusive of Integration, Yield Analysis, Product Engr, Electrical Test, & Failure Analysis Responsible for 28 person group, + $ 1M budget, & group development.My responsibilities included working with Process Engineering to eliminate the largest Yield, Speed, and Reliability constraints. Led development for an Engineering lot analysis system to support experiments, process changes, & verification of process changes. Developed a Failure analysis Prioritization system to ensure the limited Failure analysis capacity was effectively used to provide the maximum benefit. Supported new Failure Analysis equipment introduction to provide better and more capableRoot cause analysis. Developed new metrics to maximize die out through Final Test, maximizing and balancing Sort vs Speed bin concerns Led effort to generate accurate yield Pareto, develop viable solutions, & prioritize yield & reliability constraints to achieve all yield goals.I utilized yield models to compare different products & processes to identify discrepancies from defect contributions.