Tommy Miles Email and Phone Number

• Deep submicron L3 Cache block tech lead on AMD’s EPYC®7003, 7004, 9004, 9005, and next gen series processors.

Manages the development and architecture of our global data, electrical, and software systems integration. He is responsible for overseeing the development and production of remote monitoring systems, database and data management across Envirofit’s business units, and leads Envirofit’s SmartGas electrical hardware design, software development, and communications architecture. He develops strategies for managing and analyzing data, as well as generating a cohesive reuse model across multiple international teams with differing complex objectives.

• Project lead, architect, and top level owner of a memristor characterization vehicle ASIC in 180nm. A unique multi-fab approach using a low cost ASIC and post processed production scale device from a second fab to enable quick, reliable, high throughput, and low parasitic testing of critical dimension memory devices. Responsible for establishing and implementing new team policies and methodologies leading to the success of resource limited projects though the development of new architectures, tools, and testing strategies.• Developed a web based metrics database to enable multiple design teams to have greater visibility into key performance indicators and quality of results.• Responsibilities: development of tools, strategies, and methodologies for 16nm ASIC. Top level ASIC architecture, design, and analysis. Verification and test plan development and execution. ASIC turn on and bring up including system level definition and execution.• Program manager of a multi-disciplinary team developing a DDR memory emulation system with primary focus on scope, schedule, and resource balancing to prioritize and enable efficient project execution.• Streamlining of strategic planning processes through the development of custom analysis tools.

• Array implementation lead of a 2MB L2 cache in 28nm bulk. Developed and maintained methodologies that quickly adapt to changing design needs ranging from RTL to analysis.• Project manager and implementation lead for an 8MB Level-3 cache for 32nm Opteron 6200 and 6300 series, the world's first 16-core x86 server processor.• Project manager for both a 16nm and a 20nm SRAM test chip, implementation lead and designer for both a 28nm SRAM test chip and a 32nm SER (Soft Error Rate) test chip.• Responsibilities: developing implementation strategies and methodologies, implementation and analysis of top level IP design, project level scheduling and resourcing, regular interaction and coordination between RTL, SoC, architecture, verification, circuit and physical design teams• Tasks include: IP level SAPR and semi-custom integration, signal integrity analysis with varying PVT, noise analysis, electro-migration analysis, equivalence verification, top level floor planning, and coordination between multidisciplinary teams

• Circuit and VLSI design – Implementation of the last level cache design on the 45nm Itanium® 2 (Tukwila), a quad-core 64-bit server computer processor, specifically owning the datapath interface• Tasks include: Logical design, mask design, signal integrity analysis, clock balancing, critical path analysis, equivalence verification, power reduction analysis, and the design and simulation of test methodologies for sleep voltage regulation and measurements

• Designed and implementation the L3 power grid, metal/via fill, and scan chain by using PERL scripting• Tasks include: Unit level VLSI mask design, signal integrity analysis, clock balancing, and equivalence verification