Thomas Harper Email & Phone Number

Texas

• Led product engineering team responsible for both Production and NPI of growing product portfolio.
• Member of Core teams tasked with development of DDR5 RCD and companion chip products. Interface with Design, Validation, Test, and Reliability Engineering teams to make data-based decisions ensuring on-time delivery of.
• Managed team of Product Engineers overseeing Production in Asia, responsible for interfacing with OSAT and Foundry.
• Owner of all ATE test related data from Engineering to Production.

• Joined Rambus in the early stages of Production ramp of DDR4 RCD products and was tasked with creating infrastructure to monitor and sustain yield.
• Created automated warning system for production lots with low yield or failing statistical bin limits.
• Designed and implemented system for signing off suspect lots after disposition using MS Power Automate flows.
• Developed scripts for reporting to Customers on key parameters and other critical to quality items.
• Primary resource for in-depth data analysis that requires scripting, addressing both product yield and performance.

Led the execution of high-volume semiconductor test data-integration projects for Qualtera's Silicondash software platform, providing technical support and collaborating with cross-functional teams to define product opportunities and technical strategies.

Austin, TX

Product Yield Owner for an ARM based SOC, responsible for end-to-end yield including: wafer sort, package-level ATE, and System Level Test. Also assumed role of Foundry and Technology Product Owner responsible for wafer-planning, schedules, logistics, and technology implementation.

Austin, TX

Product Yield Owner responsible for all aspects of wafer sort yield, including: forecasting future yield, driving yield improvements with foundry partners and design teams, providing final sign-off for test program changes, and reporting of yield status and issues into product teams and executive forums.

Austin, TX

Led a product and technology implementation team of engineers, responsible for K8 product introduction at Chartered Fab7 (90nm and 65nm technologies). Coordinated and led weekly meetings covering all product engineering aspects of the project. Also, responsible for communicating product status and PDE activities to the AMD-Chartered executive teams.

Austin, TX

Led a team of engineers, responsible for introduction of 90nm SOI technology nodes on K8 products. Responsible for sort and package data analysis to understand yield sensitivities and performance improvements, as well as performing product characterization and circuit sensitivity verification.

Austin, TX

Key contributor on technology implementation teams for implementing 130nm bulk technology nodes on K7 products. Performed set-up of test flows for characterization tests on Teradyne J973 testers. Owned the product qualification for multiple product/technology implementations.

Austin, TX

Supported both the Communication and Network Product Divisions at AMD as product engineer responsible for analysis of Wafer Electrical Test and Wafer Sort Yield data.

Austin, TX

Supported all products and technologies as product engineer responsible for disposition of Wafer Electrical Test and Wafer Level Reliability failures at final WET.

Austin, TX

Worked with the F15 reliability engineer to develop and characterize Wafer Level Reliability tests, coding the WLR tests for the Keithley S900 testers, running the tests and analyzing the resulting data.

Bachelor'S Degree, Electrical Engineering, Solid State Devices

Associate'S Degree, Science, Engineering Prep