Tom Spyrou Email & Phone Number

California, United States

La Jolla, CA, US

Chief Architect and Technical Project Manager of the DARPA funded OpenROAD initiative.https://theopenroadproject.org/

San Diego, CA, US

Precision Innovations Inc. is an expert Electronic Design Automation consulting company focused on Open Source EDA tool feature development and expert EDA tool flow development, both open source and commercial. Precision Innovations is a DCAA compliant company and is registered with sams.gov enabling it to work efficiently under government contracts.

Santa Clara, California, US

Altera is now part of Intel!

Working on projects to advance the state of the art in Altera's design software and hardware. One focus area is the architecture and implementation of TimeQuest2, a new parallel and incremental STA engine optimized for the needs of FPGA's including an innovative CRPR algorithm. Other focus areas are the modelling of complex FPGA hardware components, the.

Santa Clara, California, US

I worked on the Static Timing Analysis and Timing Closure of the largest and most complex SOC's. This involved working embedded with design teams and also on internal EDA applications. I also drove an effort to utilize openCL to add parallel capability to critical applications utilizing both CPU and GPU processors.

San Jose, California, US

The technology from Precision Software Development was acquired by Cadence. This technology was related to the parallel processing of key EDA algorithms and an approach for applying parallel processing to legacy code. Within Cadence I have been driving the parallel processing effort utilizing Precison Software’s IP and have created a shared cross-platform.

Santa Barbara, CA, US

Precision Software is a company I started to provide high value product marketing and software development services to Semiconductor and EDA Companies. I worked with Semconductor Companies and EDA Companies to improve their electrical analysis and design software capabilities. For the Semiconductor companies I actively participated in the architecture of.

Responsible for Product Development in a 15 person start-up. Managed 8 software developers. Worked closely with CTO to turn product vision into product specification and implementation. Focus on predictable scheduling, repeatable process, and quality improvement. I supported financing by visiting with Venture Capitalists. I supported business requirements.

US

Acquired by Cadence June 2002.Responsibility over Simplex products for Signal Electro-migration and Power Grid Analysis, Delay Calculation and Signal Integrity. Position included direct management of R&D and cross-functional responsibility for the product line with revenue targets. I worked with Marketing on the initial roll-out of Signal-Storm to the.

Product focused on delivering a next generation RTL design and debug system capable of estimating RTL Area and Performance before Logic Synthesis. The system also had RTL, Mixed, and Gate Level Floor-planning and Placement technology. I was responsible for running an R&D organization of about 25 engineers. My challenge was entering a start-up company after.

San Jose, California, US

Responsibility for Cadence’s Static Timing technology including Pearl and Ambit timing products. Also had responsibility for the Place and Route Database group which included the team developing the next generation Open Access database. The combined organization had about 65 people.

Sunnyvale, California, US

Responsible for team of 5 people developing Synopsys’ core static timing engine which was used in PrimeTime. This role included responsibility for deployment of a shared static timing engine based on PrimeTime for both the Chip Architect Floor-planner and the Next Generation Synthesis System. I lead the development team and the design of the key.

VLSI Spun off Compass, same position new company.Sole developer of VLSI's Static Timing Verifier. VLSI was the first ASIC company to allow static timing sign-off of chips with this technology in 1990. Expanding responsibilities in to R&D Management of the RTL Synthesis Team and Timing Teams.

Eindhoven, Noord-Brabant, NL

Sole developer of VLSI's Static Timing Verifier. VLSI was the first ASIC company to allow static timing sign-off of chips with this technology in 1990. Every digital chip which went through VLSI was signed off with this timing technology.

Houston, Texas, US

Developed various applications for the ASIC Design Center's CAD group including delay calculation.

Ms, Engineering Management

Bs, Electrical And Computer Engineering

Education record