Tom Spyrou Email and Phone Number
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Experienced Software Technologist and Leader. Emphasis on performance tuning of applications and parallel processing. Seasoned software project manager using best in class continuous delivery methodology. EDA Technologist with Deep knowledge of Static Timing Analysis and Timing Closure of bleeding edge designs.Specialties: Parallel Processing, Multi Core/Threaded and Distributed Software Development. Complex Application Architecture. Complex Project Distributed Team Engineering Management. Continuously Delivery. Static Timing Analysis. VLSI SOC Prototyping and Floorplanning. Electrical and Timing Analysis of Digital Circuits. Patents and Intellectual Property. Complex Project Management. Large software team management.
Precision Innovations Inc
View- Website:
- precisioninno.com
- Employees:
- 15
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PresidentPrecision Innovations IncCalifornia, United States -
Chief Architect And Technical Project Manager Of OpenroadUniversity Of California San Diego Jul 2019 - PresentLa Jolla, Ca, UsChief Architect and Technical Project Manager of the DARPA funded OpenROAD initiative.https://theopenroadproject.org/ -
PresidentPrecision Innovations Inc Jul 2019 - PresentSan Diego, Ca, UsPrecision Innovations Inc. is an expert Electronic Design Automation consulting company focused on Open Source EDA tool feature development and expert EDA tool flow development, both open source and commercial. Precision Innovations is a DCAA compliant company and is registered with sams.gov enabling it to work efficiently under government contracts. -
Distinguished ArchitectIntel Corporation Jan 2016 - Jul 2019Santa Clara, California, UsAltera is now part of Intel! -
Distinguished Architect, Office Of The CtoAltera Dec 2012 - Dec 2015Working on projects to advance the state of the art in Altera's design software and hardware. One focus area is the architecture and implementation of TimeQuest2, a new parallel and incremental STA engine optimized for the needs of FPGA's including an innovative CRPR algorithm. Other focus areas are the modelling of complex FPGA hardware components, the CAD flow for FPGA design, and the Quartus compiler's hierarchical data model and parallel programming infrastructure.Altera Technical Symposium's chief software judge.
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FellowAmd Sep 2011 - Dec 2012Santa Clara, California, UsI worked on the Static Timing Analysis and Timing Closure of the largest and most complex SOC's. This involved working embedded with design teams and also on internal EDA applications. I also drove an effort to utilize openCL to add parallel capability to critical applications utilizing both CPU and GPU processors. -
Distinguished EngineerCadence Design Systems Oct 2006 - Sep 2011San Jose, California, UsThe technology from Precision Software Development was acquired by Cadence. This technology was related to the parallel processing of key EDA algorithms and an approach for applying parallel processing to legacy code. Within Cadence I have been driving the parallel processing effort utilizing Precison Software’s IP and have created a shared cross-platform framework for multi-threading and TCP/IP based distributed processing. I am also responsible for driving utilization of parallel processing across a 500 person organization by architecting solutions and prioritizing projects based on their value to the overall business and customer base. Starting in 2008 I began to also manage the worldwide R&D group developing Hierarchical Design Solutions in the Encounter Digital Implementation System. This responsibility was over a team of 70 engineers based in the U.S., India, and China. The responsibility included executive sponsorship and relationship management for top accounts. -
President/Principal ConsultantPrecision Software Development Inc. Mar 2004 - Oct 2006Santa Barbara, Ca, UsPrecision Software is a company I started to provide high value product marketing and software development services to Semiconductor and EDA Companies. I worked with Semconductor Companies and EDA Companies to improve their electrical analysis and design software capabilities. For the Semiconductor companies I actively participated in the architecture of their chip design flow and chip design trade-offs. For the EDA companies I developed code and helped with Product Marketing and Business Development. I used the consulting work to fund my own IP development and developed several patents and code in the area of parallel processing and parallel EDA algorithms. This IP was acquired by Cadence in October of 2006. -
Vice President Of EngineeringCiranova Inc Nov 2002 - Mar 2004Responsible for Product Development in a 15 person start-up. Managed 8 software developers. Worked closely with CTO to turn product vision into product specification and implementation. Focus on predictable scheduling, repeatable process, and quality improvement. I supported financing by visiting with Venture Capitalists. I supported business requirements by making worldwide customer visits to promote the tool and explain its significance and value. The Software is a next generation analog layout and analysis system.
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Senior Product DirectorSimplex Solutions Nov 2001 - Nov 2002UsAcquired by Cadence June 2002.Responsibility over Simplex products for Signal Electro-migration and Power Grid Analysis, Delay Calculation and Signal Integrity. Position included direct management of R&D and cross-functional responsibility for the product line with revenue targets. I worked with Marketing on the initial roll-out of Signal-Storm to the market. This included creating presentations, meeting with editors of EDA trade journals, and training the sales force and AEs on how to engage with the technology. I also made worldwide trips to present the technology to key customers and explain its significance in the design flow. My product responsibility accounted for about 80% of Simplexs software revenue. I started several key initiatives in the analysis products to tackle new problems in nanometer design and was driving a key technical effort with the CTO on a next generation analysis product. -
Vice President Of EngineeringIntime Software Mar 2000 - Dec 2001Product focused on delivering a next generation RTL design and debug system capable of estimating RTL Area and Performance before Logic Synthesis. The system also had RTL, Mixed, and Gate Level Floor-planning and Placement technology. I was responsible for running an R&D organization of about 25 engineers. My challenge was entering a start-up company after it had executed for 18 months, helping to drive the product definition, refining the software architecture, and driving the execution of the product development. I supported financing by visiting with Venture Capitalists. I supported business requirements by making worldwide customer visits to promote InTimes products. These visits included product demonstrations followed by in depth technical analysis of the Customers design flows and how InTimes solution might help.
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Engineering Group Director, Static Timing Analysis & Ic Implementation InfrastructureCadence Design Systems Dec 1997 - Mar 2000San Jose, California, UsResponsibility for Cadence’s Static Timing technology including Pearl and Ambit timing products. Also had responsibility for the Place and Route Database group which included the team developing the next generation Open Access database. The combined organization had about 65 people. -
R&D Manager, Core Timing TechnologySynopsys Inc. Feb 1996 - Nov 1997Sunnyvale, California, UsResponsible for team of 5 people developing Synopsys core static timing engine which was used in PrimeTime. This role included responsibility for deployment of a shared static timing engine based on PrimeTime for both the Chip Architect Floor-planner and the Next Generation Synthesis System. I lead the development team and the design of the key algorithms. I was also responsible for setting the direction for a joint timing solution with the IBM EDA development team, driving consensus, and managing the technical relationship. I supported Business requirements by visiting customers and working with ASIC Vendors to help achieve Sign Off status for PrimeTimes static timing analysis. -
Principal Engineer, R&D ManagerCompass Design Automation Feb 1991 - Feb 1996VLSI Spun off Compass, same position new company.Sole developer of VLSI's Static Timing Verifier. VLSI was the first ASIC company to allow static timing sign-off of chips with this technology in 1990. Expanding responsibilities in to R&D Management of the RTL Synthesis Team and Timing Teams.
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Principle Engineer, R&D ManagerVlsi Technology Aug 1988 - Feb 1991Eindhoven, Noord-Brabant, NlSole developer of VLSI's Static Timing Verifier. VLSI was the first ASIC company to allow static timing sign-off of chips with this technology in 1990. Every digital chip which went through VLSI was signed off with this timing technology. -
Software EngineerDigital Equipment Corp 1987 - 1988Houston, Texas, UsDeveloped various applications for the ASIC Design Center's CAD group including delay calculation.
Tom Spyrou Skills
Tom Spyrou Education Details
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Santa Clara UniversityEngineering Management -
Carnegie Mellon UniversityElectrical And Computer Engineering -
Upper Darby High School
Frequently Asked Questions about Tom Spyrou
What company does Tom Spyrou work for?
Tom Spyrou works for Precision Innovations Inc
What is Tom Spyrou's role at the current company?
Tom Spyrou's current role is President.
What is Tom Spyrou's email address?
Tom Spyrou's email address is to****@****rou.com
What is Tom Spyrou's direct phone number?
Tom Spyrou's direct phone number is +1.408.544*****
What schools did Tom Spyrou attend?
Tom Spyrou attended Santa Clara University, Carnegie Mellon University, Upper Darby High School.
What are some of Tom Spyrou's interests?
Tom Spyrou has interest in Disaster And Humanitarian Relief.
What skills is Tom Spyrou known for?
Tom Spyrou has skills like Eda, Asic, Soc, Static Timing Analysis, Tcl, Semiconductors, Vlsi, Ic, Software Development, Debugging, Rtl Design, Verilog.
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